Nanosheet Stacks With Dielectric Isolation for Precise Gate Patterning
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Solution Overview
Problem
Current techniques for forming nanosheet transistor structures face challenges in patterning gate conductors due to tight spacing between nanosheets, leading to over-etching issues and complexity in maintaining the N-to-P boundary, especially as device sizes increase.
Innovation Solution
The implementation of a reversible crosslinking organic planarization layer (OPL) reflow with a novel shallow trench isolation (STI) structure, which forms a dielectric bar or isolation layer to protect nanosheet channel layers and control the gate dielectric layer placement, ensuring precise positioning of the gate dielectric layer over one type of FET while avoiding over-etching under the OPL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning techniques are used for gate conductors, then the manufacturing process is simpler, but over-etching occurs and the N-to-P boundary cannot be maintained precisely
Solution Approach 1:
The patent applies preliminary action by forming the dielectric isolation layer on the nanosheet stacks before gate conductor patterning. This pre-formed isolation structure serves as a protective barrier that prevents over-etching during subsequent patterning steps, thereby maintaining precise N-to-P boundaries without requiring complex patterning process adjustments.
Solution Approach 2:
The dielectric isolation layer acts as an intermediary element between the nanosheet channel layers and the gate conductor. This intermediate structure protects the underlying nanosheets during etching processes while enabling precise definition of the N-to-P boundary, resolving the contradiction between precision and process simplicity.
2Use of energy by moving object
If device size is increased to improve performance, then power consumption decreases, but over-etching issues and boundary maintenance complexity increase
Solution Approach 1:
By pre-forming the dielectric isolation layer before gate patterning, the patent enables scaling to larger device sizes while maintaining precise boundaries. The isolation layer is established in advance to protect against etching variations that would otherwise worsen with increased device dimensions.
3Area of stationary object
If tight spacing between nanosheets is maintained to increase device density, then chip area utilization improves, but over-etching and boundary control become more difficult
Solution Approach 1:
The dielectric isolation layer serves as a protective intermediary that enables tight nanosheet spacing while preventing over-etching. By placing this isolation layer on the nanosheet stacks before patterning, the patent maintains high device density without the usual penalties of increased patterning complexity.
Data Source
AI summary
A semiconductor structure comprises a first nanosheet stack comprising one or more first nanosheet channel layers and a first dielectric isolation layer over the one or more first nanosheet channel layers, a second nanosheet stack comprising one or more second nanosheet channel layers and a second dielectric isolation layer over the one or more second nanosheet channel layers, and a gate dielectric layer disposed over a top surface of one of the first dielectric isolation layer and the second dielectric isolation layer.