Adjacent Nanosheet Stacks With Differentiated Sheet Height
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, existing methods struggle to optimize the performance of n-type and p-type field effect transistors (NFETs and PFETs) on the same substrate by providing uniform semiconductor layer thickness, leading to suboptimal electrical performance and wafer acceptance testing (WAT) results.
Innovation Solution
A one-step etch process is employed to create nanosheets with differentiated thicknesses for NFET and PFET devices, allowing tunable performance by selectively etching semiconductor layers with high-etch selectivity, using a mixed composition interface layer to differentiate etch rates between n-type and p-type regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform semiconductor layer thickness is used for NFET and PFET devices, then manufacturing process is simplified, but electrical performance is suboptimal
Solution Approach 1:
The patent applies local quality by creating different semiconductor layer thicknesses in different regions of the same substrate. Specifically, first semiconductor layers are formed with a first thickness for NFET devices while second semiconductor layers are formed with a second thickness for PFET devices. This allows each device type to have optimized electrical performance while using a unified manufacturing process flow.
2Reliability
If differentiated semiconductor layer thicknesses are created for NFET and PFET devices, then electrical performance is optimized, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor layer formation process into distinct stages. First, a multi-layer stack is formed containing alternating sacrificial and semiconductor layers. Then, selective removal of sacrificial layers creates differentiated thickness regions. Finally, planarization achieves the desired thickness distribution. This segmented approach enables differentiated thickness without requiring completely separate manufacturing processes.
Solution Approach 2:
The patent applies parameter changes by modifying the etch selectivity parameters during the selective removal process. By controlling the etch selectivity between sacrificial and semiconductor layers, the process achieves different thicknesses for NFET and PFET regions. Additionally, planarization parameters are adjusted to achieve the final differentiated thickness distribution while maintaining process integration.
3Productivity
If minimum feature sizes are reduced for increased integration density, then more components can be integrated, but additional manufacturing and performance problems arise
Solution Approach 1:
The patent applies dimensionality change by transitioning from two-dimensional planar transistors to three-dimensional nanosheet structures. The semiconductor layers are formed as vertically stacked nanosheets with controlled thicknesses, enabling continued scaling and integration density improvement while maintaining manufacturability through the multi-layer stack formation and selective removal process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances NFET and PFET performance by reducing doping effects and improving channel resistance, resulting in better electrical performance and wafer acceptance testing (WAT) outcomes.
Implementation Method 1
A one-step etch process is employed to create nanosheets with differentiated thicknesses for NFET and PFET devices, allowing tunable performance by selectively etching semiconductor layers with high-etch selectivity
Data Source
AI summary
A semiconductor device including a substrate including a first device region and a second device region. A first type device is present in the first device region, the first type device including a first stack of nanostructures, and a first gate stack around each first nanostructure of the first stack of nanostructures, wherein said each first nanostructure of the first stack of nanostructures has a first height. A second type device is present in the second device region, the second type device including a second stack of nanostructures, and a second gate stack around each second nanostructure of the second stack of nanostructures, wherein said each second nanostructure of the second stack of nanostructures has a second height. The second height is different than the first height.