Nanosheet Transistor Stepped Structure for Channel Count Control

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Solution Overview

Problem

The integration of transistors with different functions in semiconductor integrated circuits faces challenges, particularly in achieving efficient manufacturing of transistors with varying channel lengths and numbers of functional nanosheets in different regions, leading to issues such as low product yield and increased complexity.

Innovation Solution

A semiconductor structure design and manufacturing method that includes a stepped structure and sidewall spacers to control the number of functional nanosheets in different regions, allowing for varying channel lengths and numbers of functional channels, thereby improving integration and yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If transistors with different functions are integrated in the same semiconductor structure, then device functionality and performance are improved, but manufacturing complexity increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The semiconductor structure is divided into first and second regions with different transistor configurations. The first region contains transistors with first channel lengths and the second region contains transistors with second channel lengths, allowing different functions to be integrated without requiring entirely separate manufacturing processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the semiconductor structure are given different local characteristics - the first region has transistors optimized for one function while the second region has transistors optimized for another function, achieving versatility through spatial differentiation rather than complex global design.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If transistors with varying channel lengths are manufactured, then device performance is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedevice performanceVSAvoidchannel length control
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The structure segments transistors into two distinct groups with different channel lengths, where each group is manufactured using the same overall process flow but with region-specific parameters, reducing the precision burden compared to continuous variation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of manufacturing transistors with all possible channel length variations, the invention uses two discrete channel length values (first and second channel lengths), which is sufficient for the application requirements while significantly simplifying manufacturing precision requirements.

Inventive Principle:
Principle #16Partial or excessive action

3Adaptability or versatility

If different numbers of functional nanosheets are used in different regions, then transistor functionality is improved, but device complexity increases

Engineering Contradiction:
Improvetransistor functionalityVSAvoidnanosheet configuration
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The semiconductor structure segments nanosheet configurations by region, with the first region containing transistors with a first number of functional nanosheets and the second region containing transistors with a second number of functional nanosheets, enabling functional differentiation through spatial segmentation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250234603A1Semiconductor structure and manufacturing method thereof
Publication Date: 2025.07.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250234603A1 patent drawing
  • US20250234603A1 patent drawing
  • US20250234603A1 patent drawing

AI summary

A semiconductor structure includes a plurality of nanosheets, a gate structure, an S/D structure, a stepped structure, and a sidewall spacer. The plurality of nanosheets is disposed over a substrate, wherein the substrate extends along a first direction, and the nanosheets are arranged along a second direction substantially perpendicular to the first direction. The gate structure is disposed over the substrate, wherein the gate structure is disposed between and surrounding the nanosheets. The S/D structure is disposed adjacent to the gate structure and the plurality of nanosheets. The stepped structure is disposed below the S/D structure, wherein the stepped structure overlaps at least one of the nanosheets along the first direction. The sidewall spacer is disposed between the stepped structure and the at least one of the nanosheets. A method of manufacturing the semiconductor structure is also provided.