Nanosheet Transistor Channel Strain via Modified Sacrificial Gate
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Solution Overview
Problem
In nanosheet transistors, it is challenging to maintain strain in the channel region due to the limited area available, which affects the mobility of charge carriers and device performance, as subsequent processing often relaxes the desired strain.
Innovation Solution
A method is introduced where a sacrificial gate is modified to induce strain in the nanosheet stack, which is then fixed by forming merging source/drain regions, allowing the sacrificial gate to be replaced with a conductive gate without losing the induced strain, thereby maintaining the strain in the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a sacrificial gate is modified to induce strain in the nanosheet stack, then charge carrier mobility is improved, but subsequent processing steps tend to relax the desired strain
Solution Approach 1:
The sacrificial gate is modified with a strain-inducing layer before the final gate is formed. This preliminary strain induction ensures that the desired strain state is established early in the fabrication process, and subsequent processing steps are designed to preserve rather than relax this strain, thereby maintaining charge carrier mobility improvements throughout device operation
Solution Approach 2:
A strain-inducing layer is introduced as an intermediary between the sacrificial gate and the nanosheet stack. This intermediary layer serves as a strain source that can be selectively removed or modified, allowing strain to be transferred to the channel region while the sacrificial gate itself can be replaced with the final conductive gate structure
2Area of stationary object
If the nanosheet stack area is limited, then device density is increased, but the ability to maintain strain in the channel region is reduced
Solution Approach 1:
The strain-inducing layer is selectively positioned only in regions where strain is needed in the channel, rather than uniformly across the entire device structure. This localized approach allows effective strain induction in the critical channel region while minimizing the overall device footprint and maintaining high device density
Solution Approach 2:
The strain induction mechanism is implemented in the vertical dimension through the sacrificial gate and strain-inducing layer structure, rather than requiring extended lateral dimensions. This vertical strain induction approach allows effective channel strain in a compact lateral footprint, thereby maintaining both device density and charge carrier mobility
3Ease of manufacture
If the sacrificial gate is replaced with a conductive gate, then device functionality is completed, but the induced strain may be lost
Solution Approach 1:
The strain-inducing layer is integrated into the sacrificial gate structure before the final gate formation. This preliminary integration ensures that the strain-inducing functionality is established early, and the subsequent replacement of the sacrificial gate with the conductive gate is designed to preserve the strain-inducing layer, thereby maintaining both device functionality and strain
Solution Approach 2:
The sacrificial gate material is selectively removed or replaced with the conductive gate material, while the strain-inducing layer is preserved. This selective extraction allows the sacrificial gate to serve its temporary purpose of defining the channel region and inducing strain, then be replaced with the final functional gate without losing the strain-inducing capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the mobility of charge carriers by maintaining strain in the channel region, improving device performance by enhancing electron and hole mobility without relaxing the strain during subsequent processing steps.
Implementation Method 1
modifying the sacrificial gate over the nanosheet stack, wherein the modification causes a phase transition to induce strain in the one or more layers
Data Source
AI summary
Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.