Nanosheet Strained Channel FETs for Sub-10 nm Mobility
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Solution Overview
Problem
III-V semiconductor-based MOSFETs face a tradeoff between high mobility and short-channel performance due to the use of crystalline buffer layers, which limit their application to relatively long gate lengths and introduce processing difficulties for sub-10 nm technologies.
Innovation Solution
A field effect transistor design featuring a nanosheet stack with individually gated crystalline semiconductor channels, crystalline gate dielectric layers, and crystalline gate layers, eliminating amorphous materials at the interface to reduce surface roughness scattering and maintain strain, allowing for high mobility and improved short-channel behavior without crystalline buffer layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If crystalline buffer layers are used to reduce surface roughness scattering and improve mobility, then channel mobility is improved, but short-channel performance degrades due to increased separation between gate electrode and channel inversion layer
Solution Approach 1:
The patent removes the crystalline buffer layer (such as InP) that traditionally separates the channel from the gate dielectric. By extracting this intermediate layer, the gate electrode is brought into direct contact with the channel inversion layer, eliminating the separation that degraded short-channel performance while maintaining the mobility benefits through alternative surface roughness mitigation strategies
Solution Approach 2:
The patent introduces an amorphous buffer layer as an intermediary between the crystalline channel and the gate dielectric. This amorphous layer serves as a mediator that reduces surface roughness scattering to maintain mobility without the detrimental effects of thick crystalline buffer layers, enabling both high mobility and good short-channel performance
2Speed
If III-V semiconductor channel materials are used to achieve high mobility through low electron effective mass, then channel mobility is improved, but surface roughness scattering increases due to penetration of electron wavefunctions into non-crystalline gate dielectric layers
Solution Approach 1:
The patent changes the physical state parameter of the buffer layer from crystalline to amorphous. This parameter change allows the buffer layer to provide surface smoothing functionality without the rigid lattice structure that causes surface roughness scattering, thereby maintaining high mobility while reducing the harmful scattering effect at the interface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high channel mobility and good short-channel performance, suitable for sub-10 nm technologies, by minimizing surface roughness scattering and maintaining strain in the channel and gate layers, thus eliminating the mobility-EOT tradeoff.
Implementation Method 1
The nanosheet stack is strained from lattice mismatch between ones of the layers thereof
Data Source
AI summary
A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.