Nanosheet Threshold Voltage Control via Digital Etch
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Solution Overview
Problem
As semiconductor technology scales, the reduction in channel length of MOSFETs leads to threshold voltage variation, affecting leakage power and operation of high-performance transistors due to parasitic diodes, making it challenging to maintain effective gate control over the channel.
Innovation Solution
A method involving the formation of a nanosheet stack with sacrificial layers and nanowires, followed by partial etching, digital etching of one side, and deposition of a high-k metal gate within recesses formed by removing sacrificial layers, allowing precise control of threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel length is reduced to scale semiconductor technology, then transistor density and integration are improved, but threshold voltage control deteriorates due to parasitic diodes affecting gate control
Solution Approach 1:
The patent applies local quality by creating asymmetric channel structures where different portions of the channel have different lengths. Specifically, the channel is engineered with a first portion and a second portion having different lengths, allowing localized optimization of threshold voltage characteristics in specific regions while maintaining high overall integration density. This enables precise control of threshold voltage by modifying channel length at specific locations rather than uniformly across the entire device.
2Volume of moving object
If channel length is reduced, then device miniaturization is achieved, but leakage power increases due to loss of gate control over the channel
Solution Approach 1:
The patent reduces leakage power by implementing local quality variations in the channel structure. By creating asymmetric channel lengths where certain regions have extended channel portions, the gate control is enhanced locally at critical points. This asymmetric design allows the device to maintain compact overall dimensions while preventing carrier leakage through strategically positioned longer channel sections that strengthen the energy barrier in high-leakage regions.
Solution Approach 2:
The patent employs dynamics by making the channel structure adjustable and non-uniform. The asymmetric channel design with varying lengths in different portions allows the device to dynamically optimize its electrical characteristics. The different channel lengths create varying electric field distributions that can be tuned to suppress leakage currents while maintaining drive current, effectively making the channel's electrical behavior adaptable to different operating conditions despite fixed physical dimensions.
Data Source
AI summary
A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.