Gate-All-Around Nanosheet Transistors With Bottom Dielectric Isolation
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Solution Overview
Problem
Existing gate-all-around (GAA) transistors face challenges in achieving optimal gate control, reducing leakage current, and improving scaling capability for advanced integrated circuit (IC) applications.
Innovation Solution
The implementation of n-type and p-type metal-oxide-semiconductor field effect transistors (MOSFETs) with a bottom dielectric layer in an n-type well region, which isolates the source/drain features from the underlying well region, reducing leakage currents and enhancing DC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-all-around (GAA) transistors are implemented to improve gate control, then gate-channel coupling is increased, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that wrap completely around the channel region. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sidewalls), significantly improving gate-channel coupling and reducing short-channel effects while maintaining scalability for advanced technology nodes
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the channel region into multiple nanosheets stacked vertically, with each nanosheet forming an independent channel. This segmentation allows the device to maintain smaller lateral dimensions (improving density) while using vertical stacking to preserve manufacturing feasibility. The segmented structure also enables independent control of multiple channels through a single gate, improving productivity without proportionally increasing processing complexity
Solution Approach 2:
The patent moves from two-dimensional planar scaling to three-dimensional vertical stacking of nanosheets. This dimensional transition allows continued scaling of functional density by exploiting the vertical dimension, thereby maintaining productivity gains without being constrained by lateral lithography limits, while the regular stacked geometry simplifies manufacturing compared to irregular miniaturization
3Device complexity
If source/drain features are directly connected to the well region, then device simplicity is maintained, but off-state leakage current increases
Solution Approach 1:
The patent introduces a bottom dielectric layer as an intermediary between the source/drain features and the underlying well region. This dielectric layer acts as a barrier that blocks leakage current paths while maintaining electrical isolation. The intermediary layer prevents direct contact between oppositely doped regions, thereby eliminating junction leakage without requiring complex additional structures
Solution Approach 2:
The patent extracts the harmful direct junction between source/drain and well region by removing the direct electrical contact pathway. By taking out the direct connection and replacing it with a dielectric barrier, the leakage mechanism is eliminated while the overall device structure remains relatively simple, maintaining ease of manufacture
4Reliability
If multi-gate structures are used to reduce short-channel effects, then gate control improves, but capacitance between source/drain and bulk increases
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that wrap completely around the channel region including the bottom. This dimensional change allows the gate to control the channel from all directions, significantly improving short-channel effect control. Simultaneously, the bottom dielectric layer isolates the source/drain from the bulk, reducing parasitic capacitance that would otherwise increase with enhanced gate control
Data Source
AI summary
A semiconductor structure includes a substrate; a well region disposed in the substrate; first nanostructures suspended over and vertically arranged over the well region; second nanostructures suspended over and vertically arranged over the well region; and a gate structure wrapped around each of the first nanostructures and each of the second nanostructures. The semiconductor structure further includes a first source/drain feature and a second source/drain feature attached to opposite sides of the first nanostructures, wherein each of the first source/drain feature and the second source/drain feature includes a first bottom dielectric layer over the well region and a first doped epitaxial layer over the first bottom dielectric layer; and a third source/drain feature and a fourth source/drain feature attached to opposite sides of the second nanostructures, wherein each of the third source/drain feature and the fourth source/drain feature includes a second doped epitaxial layer over the well region.