Nanosheet Transistor Bottom Isolation Fill Layer
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Solution Overview
Problem
Current nanosheet transistor devices face challenges in achieving sufficient electrical isolation between the gate structure and the substrate, leading to potential over-etching issues and reduced dielectric thickness between the conductive gate electrode and the substrate.
Innovation Solution
A method is developed to form a nanosheet transistor device by creating a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, followed by the deposition of a stack liner and spacer layer, which allows for the formation of a conduit and a fill layer that increases electrical isolation and dielectric thickness between the gate and substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional nanosheet transistor structure is used, then the device can be fabricated with standard processes, but electrical isolation between the gate structure and substrate is insufficient leading to over-etching issues and reduced dielectric thickness
Solution Approach 1:
The device is divided into distinct segments including a bottom isolation segment, nanosheet segments, and intermediate sacrificial segments. This segmentation allows the bottom isolation segment to be specifically optimized for electrical isolation without affecting the overall device fabrication process, thereby improving reliability while maintaining manageable complexity through modular design.
Solution Approach 2:
The bottom isolation segment is formed preliminarily before the main nanosheet structure is completed. This preliminary action establishes the electrical isolation foundation early in the fabrication process, preventing over-etching issues before they occur and ensuring adequate dielectric thickness is maintained throughout subsequent processing steps.
2Reliability
If the dielectric thickness between gate and substrate is increased to reduce leakage current, then electrical isolation improves, but the device structure becomes more complex requiring additional layers and processing steps
Solution Approach 1:
The dielectric structure is segmented into the bottom isolation segment and the gate dielectric layer, with each serving a specific function. The bottom isolation segment provides the primary electrical isolation and leakage current reduction, while the gate dielectric layer maintains gate control. This segmentation allows adequate dielectric thickness to be achieved without requiring excessive overall layer complexity.
Solution Approach 2:
The bottom isolation segment acts as an intermediary element between the substrate and the nanosheet channel. It provides the necessary electrical isolation and leakage current reduction while enabling the gate structure to function properly without direct contact with the substrate, thereby reducing parasitic capacitance without proportionally increasing structural complexity.
3Reliability
If the bottom sacrificial segment is removed to form a conduit, then electrical isolation is enhanced, but the fabrication process becomes more complex requiring additional fill steps
Solution Approach 1:
The conduit is formed preliminarily by removing the bottom sacrificial segment before final gate structure assembly. This preliminary action creates the necessary space for the isolation fill material, allowing electrical isolation to be established early in the process. The subsequent fill step then completes the isolation structure without requiring complex rework of previously formed elements.
Solution Approach 2:
The bottom sacrificial segment is extracted from the structure to form the conduit. This extraction creates the void space needed for the isolation fill material, enabling enhanced electrical isolation. The sacrificial segment is temporarily incorporated into the structure and then removed at the appropriate stage, simplifying the overall fabrication process compared to attempting to form the conduit through more complex direct patterning methods.
Data Source
AI summary
A method of forming a nanosheet transistor device is provided. The method includes forming a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, wherein the segment stack is on a mesa and a nanosheet template in on the segment stack. The method further includes removing the bottom sacrificial layer to form a conduit, and forming a fill layer in the conduit and encapsulating at least a portion of the segment stack.