Nanosheet Transistor Co-Integration with Single and Multi-Gate Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in achieving higher drive currents with increasingly smaller transistor dimensions, particularly in non-planar devices like nanowire and nano-sheet transistors, which require improved gate electrostatic control and effective device width per footprint.
Innovation Solution
The method involves forming stacks of nanosheets with varying thicknesses, where a single gate structure is created for thicker nanosheets and a multi-gate structure for thinner nanosheets, using dielectric and work function metal layers to enhance gate control and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistor dimensions are reduced to increase integration density, then device footprint is reduced, but gate electrostatic control deteriorates
Solution Approach 1:
The patent transitions from planar 2D gate control to 3D non-planar gate structures (nanowire and nanosheet configurations). By wrapping the gate electrode around the channel in multiple dimensions, the gate achieves superior electrostatic control over the channel while maintaining small footprint. The gate electrode surrounds the channel region in a wraparound configuration, providing control from multiple spatial directions simultaneously.
Solution Approach 2:
The patent employs curved and wrapped gate structures instead of flat planar gates. The gate electrode is configured to wrap around nanowire channels or surround nanosheet channels, creating a curved geometrical arrangement that enhances electrostatic control. This curved configuration allows the gate to maintain close proximity to the channel from multiple angles, improving field effect control.
2Reliability
If non-planar nanowire and nanosheet structures are used to improve gate control, then electrostatic control is enhanced, but device complexity increases
Solution Approach 1:
The patent combines multiple functional layers into integrated structures. The gate electrode is merged with the gate dielectric to form a unified gate assembly that wraps around the channel. Multiple nanosheets are stacked and combined into a single channel structure, and the gate electrode consolidates control over all stacked nanosheets simultaneously, reducing the number of separate control elements needed.
Solution Approach 2:
The wraparound gate electrode structure serves multiple functions simultaneously: it provides electrostatic control over the channel, defines the active device region, and acts as a barrier to unwanted current paths. The same gate structure that provides control also serves as an isolation element, reducing the need for additional separate components.
3Reliability
If thinner nanosheets are used for multi-gate structures, then gate control is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the complete stack of alternating semiconductor and dielectric layers before any gate structure formation. This preliminary stacking establishes precise thickness control through the deposition process parameters, and subsequent processing steps work from this pre-defined foundation. The gate structures are then formed based on this predetermined stack configuration, allowing consistent thickness control across all devices.
Solution Approach 2:
The patent utilizes controlled changes in layer thickness parameters to differentiate between single-gate and multi-gate device regions. By adjusting the thickness of sacrificial layers or spacer layers during deposition, the final nanosheet thickness and gate configuration are determined. This parameter control allows precise tuning of device characteristics while maintaining manufacturing feasibility.
Data Source
AI summary
A method of forming a semiconductor device that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness; and forming a oxide layer on the first and second stack of nanosheets. The oxide layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.