Nanosheet Transistor Structure With Continuous SiGe Source/Drain Channel
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Solution Overview
Problem
Existing semiconductor structures face challenges in achieving low-external resistance and continuous material source/drain channels, which are crucial for efficient signal transmission and scalability in nanosheet transistors.
Innovation Solution
The semiconductor structure incorporates a method of forming a single continuous material source/drain channel by growing buffer silicon on lateral sides of dummy gates, annealing the source/drain epi and buffer silicon into a single continuous SiGe material, and replacing the SiGe dummy layers with a high-K metal gate (HKMG).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional source/drain structures are used in nanosheet transistors, then manufacturing is simpler, but external resistance is high which limits signal transmission efficiency
Solution Approach 1:
The method performs preliminary actions by forming buffer silicon regions and source/drain epitaxial layers before final gate formation. The buffer silicon is grown on lateral sides of dummy gates, and source/drain epi is grown on the buffer silicon, preparing the structure in advance to enable subsequent annealing that creates the single continuous material channel, thereby reducing external resistance before the actual transistor operation
Solution Approach 2:
The invention changes material parameters by transitioning from traditional segmented source/drain structures to a single continuous material channel. The annealing process transforms the source/drain epi and buffer silicon into a unified continuous SiGe material, fundamentally changing the electrical conductivity parameter and reducing external resistance by eliminating material interfaces
2Reliability
If segmented source/drain structures are used, then manufacturing is easier, but the channel is not continuous which increases resistance
Solution Approach 1:
The invention merges the source/drain epitaxial layer and buffer silicon region into a single continuous SiGe material channel through thermal annealing. This combining process eliminates the interface between separate materials, creating a unified continuous channel that reduces resistance while maintaining the necessary structural complexity for nanosheet transistor operation
Solution Approach 2:
The invention uses composite SiGe material structure where silicon and germanium are combined in specific ratios to create the single continuous channel. The source/drain epi and buffer silicon form a composite structure that, when annealed, creates a continuous SiGe material with optimized electrical properties for low resistance while maintaining structural integrity
3Reliability
If SiGe dummy layers are retained, then structural support is maintained, but resistance between channel and source/drain regions remains high
Solution Approach 1:
The method extracts and removes the SiGe dummy layers from the structure after they have served their purpose as structural templates during manufacturing. By taking out these dummy layers and replacing them with the single continuous SiGe material channel formed through annealing, the invention eliminates the high-resistance interfaces while maintaining the necessary structural support through the continuous material channel
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces resistance between the channel and the source/drain regions, enabling efficient signal transmission and improving the scalability and performance of nanosheet transistors.
Implementation Method 1
annealing the S/D epi and the buffer silicon into a single continuous material
Data Source
AI summary
A semiconductor structure includes a semiconductor structure. The semiconductor structure may include a semiconductor structure. The semiconductor structure may include a first gate with nanosheet layers of high-K metal gate (HKMG) and gate channel, a second gate with nanosheet layers of HKMG and gate channel, a source/drain (S/D) channel having a single continuous material between the first gate and the second gate, and inner spacers between the HKMG and the S/D channel.