Nanosheet Transistor Crystal Orientation for Shape Consistency
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Solution Overview
Problem
Current nanowire FET technologies face challenges in achieving consistent cross-sectional shapes, leading to imperfections such as surface roughness and uneven surfaces, which result in lower performance and increased variability, necessitating larger chip areas and higher power consumption due to design specifications accounting for manufacturing variability.
Innovation Solution
The use of improved nanowire orientation on wafers during fabrication, specifically orienting semiconductor crystalline nanosheets with {111} planes horizontal, combined with epitaxial growth and corner rounding techniques, to reduce and eliminate shape imperfections, resulting in more uniform and stable nanosheet transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional nanowire fabrication is used, then manufacturing is simpler, but nanosheet shape consistency deteriorates (surface roughness and uneven surfaces occur)
Solution Approach 1:
The patent applies parameter changes by modifying the crystal orientation parameter from conventional <100> to <111> oriented substrates. This fundamental parameter change in the substrate orientation directly influences the epitaxial growth process, resulting in nanosheets with flat top and bottom surfaces and rounded corners, thereby achieving consistent nanosheet shapes without complicating the overall fabrication process
Solution Approach 2:
The patent implements preliminary action by pre-orienting the substrate with <111> crystal orientation before initiating epitaxial growth. This preliminary preparation of the substrate ensures that subsequent nanosheet growth automatically achieves the desired shape characteristics (flat surfaces and rounded corners), eliminating the need for post-processing corrections and simplifying the manufacturing workflow
2Reliability
If nanosheet shape imperfections are present, then fabrication is easier, but transistor performance deteriorates (lower mobility and higher variability)
Solution Approach 1:
By changing the substrate orientation parameter to <111>, the patent fundamentally alters the growth characteristics of nanosheets during epitaxial processing. This parameter change ensures uniform nanosheet shapes with flat surfaces and rounded corners, directly improving transistor performance consistency and reducing variability without requiring additional manufacturing precision controls
3Manufacturing precision
If design specifications account for manufacturing variability, then reliability is maintained, but chip area and power consumption increase
Solution Approach 1:
The patent changes the substrate orientation parameter to <111>, which inherently produces nanosheets with consistent shapes and reduced variability. This parameter change eliminates the need for oversized design specifications and guard bands, allowing compact circuit design without sacrificing reliability, thereby reducing chip area while maintaining performance consistency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by reducing surface roughness, increasing mobility, and decreasing performance variability, allowing for fewer transistors to achieve the same drive strength and switching speed, thereby reducing power consumption and chip area while maintaining consistent nanosheet thickness and avoiding electric field hot spots.
Implementation Method 1
forming a column of layers on the substrate, including at least one silicon layer each spaced from a next layer below, the silicon layers being oriented such that {111} planes of the silicon layers are horizontal
Implementation Method 2
The column of layers is annealed to round the corners of the channel segment of each of the silicon layers in the column
Data Source
AI summary
The independent claims of this patent signify a concise description of embodiments. Disclosed is technology, roughly described, in which a semiconductor structure includes a substrate supporting a column of at least one (and preferably more than one) horizontally-oriented nanosheet transistor, each having a respective channel segment of semiconductor crystalline nanosheet material (preferably silicon or a silicon alloy) sheathed by gate stack material, wherein the channel segments have a diamond cubic crystal structure and are oriented such that the {111} planes are horizontal. Also disclosed is a method for fabricating such a structure, and a corrugated substrate that may be formed as an intermediate product. This Abstract is not intended to limit the scope of the claims.