Nanosheet Transistor Structure With Dielectric S/D Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of maintaining leakage current below a critical threshold in nano-sheet-based devices impedes the optimization of device performance and increases processing complexity, particularly due to weak gate control over the bottom channel and potential dopant-induced junction leakage.
Innovation Solution
Replacing portions of the source/drain features below the lowest transistor channel with a dielectric material to isolate the bottom channel, thereby minimizing charge carrier migration and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If source/drain features are extended below the lowest transistor channel to provide structural support, then device structural integrity is improved, but leakage current increases due to weak gate control and dopant-induced junction leakage
Solution Approach 1:
The patent extracts the problematic source/drain features from the region below the lowest transistor channel and replaces them with dielectric material. This removal eliminates the harmful leakage current path while preserving the necessary structural support through the dielectric material, thus resolving the contradiction between structural integrity and leakage current reduction.
Solution Approach 2:
The patent changes the material parameter in the region below the channel from conductive source/drain material to insulating dielectric material. This parameter change transforms the region from a leakage-prone conductive path to an isolating barrier, reducing leakage current while maintaining structural support through the dielectric's mechanical properties.
2Ease of manufacture
If conventional fabrication processes are used for nano-sheet-based devices, then manufacturing simplicity is maintained, but leakage current exceeds critical threshold
Solution Approach 1:
The patent incorporates the dielectric material insertion step into the existing fabrication sequence at an optimal point before final device assembly. This preliminary action integrates the leakage prevention measure seamlessly into the conventional process flow, maintaining manufacturing simplicity while achieving the required leakage current reduction below the critical threshold.
3Reliability
If gate structure is extended to provide multigate control, then gate-channel coupling is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the device structure into distinct regions with different materials: the multigate structure for active control and the dielectric-filled region below the channel for isolation. This segmentation allows each region to be optimized independently, maintaining strong gate control through the extended gate while simplifying manufacturing by using standard dielectric filling processes for the isolation region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves device performance by mitigating leakage current and threshold voltage mismatches, enhancing gate control over the channel, and reducing operational issues.
Implementation Method 1
Replacing portions of the source/drain features below the lowest transistor channel with a dielectric material to isolate the bottom channel, thereby minimizing charge carrier migration and reducing leakage current
Data Source
AI summary
A semiconductor device includes a fin on a substrate extending along a fin direction, a first and a second source/drain features on the fin. The semiconductor device also includes a stack of semiconductor layers over a first portion of the fin and between the first source/drain feature and the second source/drain feature. The semiconductor device further includes a gate structure over the stack of semiconductor layers. The gate structure extends along a gate direction perpendicular to the fin direction. Moreover, the gate structure engages with the stack of semiconductor layers. The semiconductor device includes a dielectric layer interposing between the first source/drain feature and the fin along a vertical direction, where the vertical direction is perpendicular to the fin direction and to the gate direction. The dielectric layer interfaces with the first portion of the fin and isolates the first source/drain feature from the first portion of the fin.