Nanosheet Transistor Stacks for Gate Control and Short-Channel Suppression
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Solution Overview
Problem
Existing semiconductor devices face challenges in improving gate controllability and suppressing the short channel effect as they become highly integrated.
Innovation Solution
A semiconductor device is designed with vertically stacked nano sheet channels, featuring a tri-gate structure around three surfaces of the nano sheets, and includes separate arrays of silicon and silicon germanium nano sheets at different horizontal levels, with isolation walls and common source/drain layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used for high integration, then device density increases, but gate controllability deteriorates and short channel effect worsens
Solution Approach 1:
The patent transitions from two-dimensional planar channels to three-dimensional vertically stacked nano sheet channels. Multiple thin silicon sheets are stacked in the vertical direction to form the channel, with the gate wrapping around the sheets from the sides. This dimensional change allows maintaining small footprint for high integration while achieving superior gate control through the vertical stacking configuration.
Solution Approach 2:
The channel is segmented into multiple thin silicon sheets stacked vertically, rather than using a single thick planar channel. Each nano sheet is thin enough to allow effective gate control, and the stacked configuration multiplies the effective channel width without increasing the planar footprint, thus improving both gate controllability and integration density.
2Productivity
If conventional planar transistors are scaled down, then integration density improves, but short channel effect increases
Solution Approach 1:
By stacking multiple thin nano sheets vertically, the effective channel length is extended in the vertical dimension while maintaining short horizontal dimensions for high integration. This allows the gate to control the channel more effectively through the stacked structure, suppressing short channel effects that plague scaled-down planar transistors.
Solution Approach 2:
The patent employs alternating layers of silicon (channel material) and silicon germanium (semiconductor material) in the vertical stack. The silicon germanium layers provide strain engineering to enhance carrier mobility in the silicon channel regions, improving device performance while maintaining the stacked configuration that suppresses short channel effects.
Data Source
AI summary
A semiconductor device comprises: a substrate including first and second buried source/drain layers; a first nano sheet stack including first nano sheets stacked in a direction vertical to the substrate; a second nano sheet stack including second nano sheets stacked in a direction vertical to the substrate; an isolation wall disposed between the first nano sheet stack and the second nano sheet stack; first gate covering portions of the first nano sheet stack and extending in a direction vertical to the substrate; second gate covering portions of the second nano sheet stack and extending in a direction vertical to the substrate; first common source/drain layers connected to end portions of the first nano sheets and to the first buried source/drain layers; and second common source/drain layers connected to end portions of the second nano sheets and to the second buried source/drain layers.