Nanosheet Transistor Sacrificial Gate Stability
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Solution Overview
Problem
Nanosheet transistors face defects and yield issues due to sacrificial gate structure collapse in the isolation region during the epitaxy preclean step, which undermines the formation of short gate lengths required for CMOS scaling.
Innovation Solution
The formation of wider sacrificial gate structures in the isolation region, utilizing a smaller lateral etch of p-type silicon during reactive ion etching, and the use of amorphous or polycrystalline silicon as a sacrificial pattern transfer layer, along with inner spacers that pinch-off the sacrificial gate structures to prevent undercutting and collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length is reduced to accommodate CMOS scaling, then the device density and integration are improved, but the sacrificial gate structures become mechanically unstable and collapse
Solution Approach 1:
The patent applies different etch selectivities to different regions: p-type silicon in isolation regions exhibits smaller lateral etch than undoped or n-type doped silicon in active regions. This creates locally optimized sacrificial gate structures with appropriate lengths for each region, preventing collapse in isolation regions while maintaining short gate lengths in active regions for high density
Solution Approach 2:
The patent changes the doping type parameter of the sacrificial gate material from undoped or n-type to p-type in isolation regions. This parameter change reduces the lateral etch rate during reactive ion etching, preventing undercutting and collapse of sacrificial gate structures in isolation regions while allowing short gate lengths in active regions
2Reliability
If the sacrificial gate structure length is increased in isolation region to prevent collapse, then the mechanical stability is improved, but the spacing between sacrificial gate structures decreases
Solution Approach 1:
The patent creates region-specific sacrificial gate structures where p-type silicon is used in isolation regions to create longer sacrificial gate structures for stability, while undoped or n-type doped silicon is used in active regions to maintain appropriate spacing. The different material properties locally optimize both stability and spacing requirements
3Reliability
If the inner spacers are formed to pinch-off sacrificial gate structures, then the mechanical stability and prevention of collapse is improved, but the device complexity increases
Solution Approach 1:
The patent forms inner spacers preliminarily to pinch-off the sacrificial gate structures before the epitaxy preclean step. This preliminary action prevents the undercutting and collapse that would otherwise occur during subsequent processing, eliminating the need for complex support structures or process modifications
Solution Approach 2:
The inner spacers act as intermediary elements that mechanically support the sacrificial gate structures during critical processing steps. These spacers temporarily fulfill the support function during manufacturing, allowing the sacrificial gates to maintain stability without requiring complex structural modifications to the final device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents sacrificial gate structure collapse, ensuring stable gate structures and improving the yield and quality of nanosheet transistors with short gate lengths by maintaining mechanical stability and reducing defect rates.
Implementation Method 1
The p-type amorphous or polycrystalline silicon increases the sacrificial gate structure length in the isolation region and thus reduces spacing between the sacrificial gate structures in the isolation region
Data Source
AI summary
Sacrificial gate structures are simultaneously formed in isolation regions that are wider than the sacrificial gate structures formed in the active region. The wider sacrificial gate structures are formed by taking advantage of a smaller lateral etch of p-type silicon than undoped or n-type doped silicon during reactive ion etching. Amorphous or polycrystalline silicon is used as a sacrificial pattern transfer patterning layer in the gate patterning process. The p-type amorphous or polycrystalline silicon increases the sacrificial gate structure length in the isolation region and thus reduces spacing between the sacrificial gate structures in the isolation region. During inner spacer formation, the inner spacers pinch-off all sacrificial gate structures in the isolation region preventing the shallow trench isolation structure to be undercut and thus preventing the collapsing of the sacrificial gate structures in the isolation region.