Nanosheet Transistor Gate Length Uniformity via SiGe Etch Control
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Solution Overview
Problem
Conventional fabrication methods for nanosheet or nanowire transistors result in non-uniform effective gate lengths due to geometric variations in sacrificial silicon germanium layers, affecting device performance and reliability.
Innovation Solution
The method involves forming a stack of alternating epitaxial silicon germanium and silicon layers with decreasing germanium content in each successive layer to control the etch rate, ensuring uniform etch back and consistent gate length across the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication methods use alternating sacrificial layers to offset active nanostructures, then the device structure can be formed, but the effective gate length becomes non-uniform due to geometric effects in patterning and etching
Solution Approach 1:
The patent applies local quality by varying the germanium content in each sacrificial silicon germanium layer. Specifically, the first sacrificial layer has a first germanium content, while the second sacrificial layer has a second germanium content that is lower than the first. This compositional variation creates different etch rates for each layer, allowing compensation for geometric effects and achieving uniform effective gate length across the device.
Solution Approach 2:
The patent changes the compositional parameter (germanium content) of the sacrificial layers to control etch behavior. By reducing the germanium content from the first sacrificial layer to the second sacrificial layer, the etch rate is modulated to compensate for geometric effects during patterning and etching, thereby achieving uniform gate length while maintaining the alternating layer structure.
2Ease of manufacture
If sacrificial silicon germanium layers are used with uniform composition, then the fabrication process is simplified, but the etch profile becomes non-uniform due to geometric effects
Solution Approach 1:
Instead of using uniform composition throughout, the patent introduces local quality variations by assigning different germanium contents to different sacrificial layers. The first sacrificial layer contains more germanium than the second sacrificial layer, creating tailored etch characteristics for each layer to compensate for position-dependent geometric effects.
Solution Approach 2:
The patent inverts the conventional approach of using identical sacrificial layers. Rather than making all sacrificial layers the same and accepting non-uniform etching, it makes them deliberately different in composition to achieve uniform etching results, effectively inverting the problem-solution relationship.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves uniform effective gate lengths in nanosheet or nanowire FETs, enhancing device performance and reliability by mitigating geometric-driven variability in the etch profile of sacrificial layers.
Implementation Method 1
uniform etch back of the sacrificial SiGe layers and the attendant realization of a more consistent gate length amongst the exposed semiconductor nanostructures may be achieved by offsetting the etch effects that contribute to a non-uniform etch profile with layer-specific variations in composition
Data Source
AI summary
A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content can be controlled such that voids created by removal of the silicon germanium have uniform dimensions, and the backfilling of such voids with gate dielectric and gate conductor layers proximate to silicon nanosheets or nanowires results in devices having a uniform effective gate length.