Nanosheet Transistor Inner Spacer Formation for Contact Resistance Reduction
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Solution Overview
Problem
Existing nanosheet transistor fabrication processes face challenges in forming high-quality source/drain regions due to limited single crystalline surface areas, leading to difficulties in achieving low contact resistance and desired performance characteristics.
Innovation Solution
The method involves forming self-aligned inner spacers using GeO2, which allows for epitaxial growth of source/drain regions on uncut elongated fin-shaped columns, providing a larger exposed Si channel surface area and enabling high-quality, low contact resistance S/D regions without chopping the fin-shaped columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used to form source/drain regions on nanosheet transistors, then the manufacturing process is simpler, but the contact resistance is high and performance is limited due to limited single crystalline surface areas
Solution Approach 1:
The method performs preliminary actions by forming inner spacers and preparing the substrate surface before epitaxial growth of source/drain regions. The inner spacers are formed to define precise locations and provide proper spacing, ensuring that when epitaxial growth occurs later, it happens on adequately prepared surfaces with sufficient area to achieve low contact resistance.
Solution Approach 2:
The invention transitions from two-dimensional planar contact formation to three-dimensional vertical stack structures with inner spacers. By utilizing the vertical dimension and forming inner spacers within the stack, the method creates multiple exposure surfaces for epitaxial growth, significantly increasing the total single crystalline surface area available for source/drain region formation.
2Manufacturing precision
If fin-shaped columns are chopped to form inner spacers, then inner spacers can be formed, but the exposed Si channel surface area is reduced and epitaxial growth quality deteriorates
Solution Approach 1:
The invention introduces oxide layers as intermediary materials that facilitate inner spacer formation without requiring chopping of fin-shaped columns. The oxide layers are deposited conformally and then selectively removed or transformed, creating inner spacers while preserving the integrity and surface area of the Si channel regions, thereby enabling both precise spacer formation and adequate surface area for high-quality epitaxial growth.
3Productivity
If epitaxial growth is performed on limited surface areas, then the fabrication process is faster, but the source/drain region quality is poor and contact resistance remains high
Solution Approach 1:
The method performs preliminary surface preparation actions including forming inner spacers and ensuring adequate exposed surface areas before initiating epitaxial growth. This preliminary preparation ensures that when epitaxial growth occurs, it has sufficient surface area to produce high-quality source/drain regions with low contact resistance, while the process remains efficient through optimized sequence of operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high-quality, low contact resistance source/drain regions, improving the performance of nanosheet transistors by maintaining the integrity of the elongated fin-shaped columns and enhancing epitaxial growth quality.
Implementation Method 1
Inner spacers are formed by performing a chemical reaction that includes converting an oxide of a second type of semiconductor material to an oxide of a first type of semiconductor material
Implementation Method 2
The method further includes forming, using an epitaxial growth process, S/D regions along the length (L) of the lateral sidewalls
Data Source
AI summary
Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device, wherein the fabrication operations include forming a stack over a substrate. The stack includes alternating layers of sacrificial nanosheets and channel nanosheets over a substrate. The stack further includes lateral sidewalls having a length (L) and end sidewalls having a width (W), wherein L is greater than W. Source or drain (S/D) regions are formed along the length (L) of the lateral sidewalls.