Nanosheet Transistor Design for IC Integration Density
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Solution Overview
Problem
Integrated circuits face challenges in achieving desired performance, area, and efficiency due to limitations in device size and transistor performance, particularly with reduced size devices having limited integration and efficiency.
Innovation Solution
The design incorporates a first cell with a first transistor featuring a nanosheet stack extending through a gate electrode, and a second cell with a second transistor, where nanosheets in the stacks pass through gate electrodes, allowing for optimized channel cross-sectional area and reduced resistance, enabling efficient wiring and performance optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If devices are reduced in size to achieve high degree of integration, then integration density increases, but device performance is limited
Solution Approach 1:
The patent transitions from planar 2D channels to 3D vertical nanosheet channels that pass through the gate electrode. This dimensional change allows the channel to extend in the vertical direction (first direction) while the gate electrode extends in the horizontal direction (second direction), effectively increasing the channel cross-sectional area without increasing the device footprint area, thus maintaining high integration density while improving device performance
Solution Approach 2:
The nanosheets are nested within a three-dimensional structure where multiple nanosheets are stacked vertically to form a nanosheet stack. The gate electrode surrounds and passes through this nested structure, creating a nested configuration where the channel is embedded within the gate structure. This nesting approach increases the effective channel area while maintaining compact device dimensions
2Area of moving object
If device size is reduced for high integration, then area efficiency improves, but current driving capability decreases
Solution Approach 1:
By extending the channel in the vertical dimension through nanosheets that pass through the gate electrode, the patent increases the channel cross-sectional area available for current flow. This allows more current paths to exist within the same device footprint, thereby improving current driving capability while maintaining high integration density
Solution Approach 2:
The patent employs a composite structure combining multiple nanosheets stacked vertically to form the channel. This composite channel structure provides multiple parallel conduction paths, effectively increasing the total channel area and current carrying capacity without proportionally increasing the device area, thus improving power capability while maintaining integration efficiency
3Device complexity
If traditional planar transistors are used, then device structure is simple, but resistance and capacitance are high
Solution Approach 1:
The patent replaces the traditional planar channel with a vertical nanosheet channel that passes through the gate electrode. This three-dimensional configuration reduces the channel length and optimizes the channel cross-sectional area, leading to reduced resistance and capacitance while the gate electrode fully surrounds the channel for improved control
Solution Approach 2:
The channel is segmented into multiple thin nanosheets stacked vertically rather than using a single thick planar channel. This segmentation increases the total channel surface area in contact with the gate electrode, improving gate control and reducing capacitance, while also reducing resistance by providing multiple parallel conduction paths
Data Source
AI summary
An integrated circuit may include a first cell and a second cell. The first cell includes a first transistor in which nanosheets included in a first nanosheet stack and a second nanosheet stack extend in a first direction to pass through a first gate electrode that extends in a second direction intersecting with the first direction. The second cell includes a second transistor in which one or more nanosheets included in a third nanosheet stack extends in the first direction to pass through a second gate electrode that extends in the second direction. A length of the first cell in the second direction may be greater than a length of the second cell in the second direction.