Nanosheet Transistor Bottom Isolation via Substrate Cavities
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Solution Overview
Problem
Current nanosheet transistor devices face challenges in achieving effective electrical isolation of source/drain regions from the substrate, which affects device performance and integration density.
Innovation Solution
A method involving the formation of vertical trenches and cavities in a semiconductor substrate, filled with an electrically insulating material, and epitaxial growth of source/drain regions within these trenches, avoiding direct connection to the substrate, and using dielectric spacers for isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation methods are used for nanosheet transistor source/drain regions, then fabrication process is simpler, but electrical isolation from substrate is insufficient
Solution Approach 1:
The isolation structure is segmented into multiple components: shallow trench isolation regions in the substrate, vertical trenches extending through the nanosheet stack, and cavities within the substrate. This segmentation allows each component to contribute to electrical isolation at different levels, achieving complete isolation while maintaining a systematic fabrication process
Solution Approach 2:
The invention transitions from conventional planar isolation to three-dimensional isolation by forming vertical trenches that extend through the nanosheet stack and creating cavities within the substrate. This vertical dimension provides additional isolation pathways, ensuring source/drain regions are electrically isolated from the substrate while accommodating the nanosheet device geometry
2Reliability
If source/drain regions are grown directly on substrate, then epitaxial growth is simpler, but connection to substrate occurs causing isolation failure
Solution Approach 1:
The shallow trench isolation regions are formed in the substrate before epitaxial growth of source/drain regions. This preliminary action creates isolation barriers that prevent direct substrate connection, ensuring that when source/drain regions are subsequently grown, they remain electrically isolated from the substrate throughout the fabrication process
Solution Approach 2:
The shallow trench isolation regions act as intermediary structures between the substrate and source/drain regions. These isolation regions physically separate the source/drain epitaxial growth from direct substrate contact, mediating the interaction and preventing harmful electrical connection while allowing the epitaxial growth process to proceed
3Reliability
If vertical trenches and cavities are formed for isolation, then electrical isolation is improved, but fabrication process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming shallow trench isolation regions first, then etching vertical trenches through the nanosheet stack, and finally creating cavities within the substrate. This segmentation allows each isolation component to be fabricated using optimized processes, managing overall complexity while achieving superior electrical isolation
Solution Approach 2:
The invention addresses isolation requirements by adding vertical dimensionality to the fabrication process. Vertical trenches extend through the nanosheet stack depth, and cavities are formed within the substrate volume, providing three-dimensional isolation that prevents substrate connection while managing process complexity through systematic vertical structuring
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides enhanced electrical isolation and prevents source/drain epitaxial connection to the substrate, improving device performance and integration density by ensuring effective bottom device isolation.
Implementation Method 1
The first and second cavities are filled with an electrically insulating material
Implementation Method 2
epitaxially growing first and second source/drain regions on the nanosheet channel layers
Data Source
AI summary
Self-limiting cavities are formed within a crystalline semiconductor substrate and beneath a stack of semiconductor layers used to form a nanosheet transistor device. Inner ends of the cavities merge beneath the stack while the outer ends thereof adjoin isolation regions within the substrate. The cavities are filled with electrically insulating material to provide bottom device isolation. Source/drain regions are grown in vertical trenches extending through the stack of semiconductor layers following formation of dielectric inner spacers. The bottom ends of the trenches adjoin the electrically insulating material within the cavities.