Nanosheet Transistor Structure for Junction Isolation and Epitaxial Control
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Solution Overview
Problem
The semiconductor integrated circuit (IC) industry faces challenges in processing and manufacturing complex ICs due to the scaling down process, which increases complexity and requires improved manufacturing methods.
Innovation Solution
A semiconductor device structure is developed with a stack of semiconductor layers having alternating materials with different etch selectivity and oxidation rates, forming nanostructure channels surrounded by a gate electrode, and employing multi-patterning and etching processes to create fin structures, isolation regions, and sacrificial gate structures, followed by epitaxial feature formation and gate dielectric and electrode creation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC scaling down process is implemented to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent segments the continuous semiconductor layer into discrete nanosheet channels separated by dielectric material. This segmentation enables independent processing and formation of multiple channels through a unified structure, reducing the overall processing complexity while maintaining high functional density through scaled-down dimensions
Solution Approach 2:
The patent implements a nested structure where dielectric material is positioned within and between semiconductor layers, and gate electrodes surround the nanosheet channels. This nesting approach allows multiple functional components to be integrated in a compact arrangement, achieving scaling down without proportionally increasing processing complexity
2Manufacturing precision
If alternating semiconductor layers with different etch selectivity and oxidation rates are used to form nanosheet channels, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by selecting specific semiconductor materials (e.g., Si, SiGe, SiC) for different layers based on their etch selectivity and oxidation rates. Each layer is locally optimized for its intended function, enabling precise formation of nanosheet channels through selective etching while maintaining a relatively simple overall transistor structure
Solution Approach 2:
The patent utilizes parameter changes in material properties (etch selectivity, oxidation rates) to achieve precise nanostructure formation. By controlling these material parameters, the patent enables differentiated processing of adjacent layers through standard etching techniques, improving manufacturing precision without requiring complex additional processing steps
3Manufacturing precision
If multi-patterning processes are employed to create intricate transistor structures, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent performs preliminary action by pre-forming the alternating semiconductor and dielectric layer structure before the final patterning step. This preliminary structuring enables subsequent multi-patterning processes to work on a pre-organized substrate, reducing the number of iterative patterning steps needed and improving overall production efficiency while maintaining high manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances processing efficiency and reduces complexity by enabling precise formation of nanostructure transistors, improving junction isolation and preventing poly on OD edge (PODE) bottom epitaxial feature bridges, thus supporting advanced IC manufacturing.
Implementation Method 1
recessing exposed portions of the stack of semiconductor layers not covered by the sacrificial gate electrode to expose first and second well portions
Implementation Method 2
forming a first dielectric layer on the first and second well portions and in the cavities
Implementation Method 3
forming an epitaxial feature over the second well portion
Data Source
AI summary
Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a semiconductor layer disposed over a substrate, and the semiconductor layer has a first end and a second end opposite the first end. The structure further includes an epitaxial feature disposed over the substrate, and the epitaxial feature is electrically connected to the first end of the semiconductor layer. The structure further includes a first dielectric layer disposed over the substrate, and the first dielectric layer is in contact with the second end of the semiconductor layer. The structure further includes a contact etch stop layer disposed on and in contact with the first dielectric layer and an interlayer dielectric layer disposed on and in contact with the contact etch stop layer.