Nanosheet Transistor Source/Drain Liner Layout for Short-Channel Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling and maintaining reliability due to short channel effects and limited current control, particularly in multi-gate transistors with three-dimensional channels.
Innovation Solution
The semiconductor device incorporates a design with a lower pattern and sheet patterns, featuring gate structures, source/drain recesses with a bottom insulating liner, and source/drain patterns, where the vertical distance between the topmost portion of the insulating liner and the bottom of the recess is controlled to enhance element performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is reduced to scale down the transistor, then the transistor density is improved, but the short channel effect worsens
Solution Approach 1:
The patent transitions from planar 2D channel to three-dimensional multi-gate structures (FinFET, nanowire, nanosheet) where the gate wraps around the channel in vertical and lateral dimensions. This dimensional change provides superior electrostatic control over the channel, enabling effective suppression of short channel effects even as channel length is reduced for higher density transistors
2Reliability
If the gate length is increased to suppress short channel effect, then the reliability is improved, but the current control ability worsens
Solution Approach 1:
By implementing multi-gate structures where the gate electrode wraps around the channel region in three dimensions (e.g., top, sidewalls), the patent achieves enhanced electrostatic control that suppresses short channel effects without requiring increased gate length. The vertical and lateral gate coverage provides superior field effect control, improving current modulation capability while maintaining scaled dimensions
3Reliability
If the bottom insulating liner thickness is increased to prevent diffusion, then the reliability is improved, but the vertical space for source/drain recess worsens
Solution Approach 1:
The patent optimizes the thickness parameter of the bottom insulating liner to achieve the minimum required value that prevents unwanted diffusion while maximizing the remaining vertical space for source/drain recess formation. This parameter optimization balances diffusion barrier functionality with the need for adequate recess depth to accommodate source/drain structures
Data Source
AI summary
There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device comprising an active pattern including, a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction, wherein the lower pattern includes a semiconductor material, a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction, wherein each of the plurality of gate structures includes a gate electrode and a gate insulating film, a source/drain recess between adjacent ones of the gate structures, wherein a bottom of the source/drain recess is in the lower pattern, a bottom insulating liner in the bottom of the source/drain recess, and a source/drain pattern in the source/drain recess and on top of the bottom insulating liner.