Nanosheet Transistor Co-Integration with Embedded Memory
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Solution Overview
Problem
Current semiconductor device fabrication processes face challenges in efficiently integrating nanosheet transistors, on-chip embedded memory, and extended-gate transistors on the same substrate, particularly in achieving optimal device density and performance while managing gate voltage thresholds.
Innovation Solution
The method involves forming a nanosheet stack with alternating layers of sacrificial and non-sacrificial nanosheets, replacing sacrificial nanosheets with conductive gates, and creating extended-gate structures to enhance gate voltage tolerance, allowing for the co-integration of nanosheet FETs, on-chip embedded flash memory, and EG transistors on a single substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet transistors are used to increase device density, then device density and performance are improved, but manufacturing complexity increases due to the need for alternating sacrificial and non-sacrificial nanosheet layers
Solution Approach 1:
The nanosheet stack is segmented into alternating sacrificial and non-sacrificial layers, allowing selective removal of sacrificial layers to create gate-all-around structures. This segmentation enables complex 3D transistor architectures to be built from simpler layered components, improving device density while managing manufacturing complexity through modular fabrication
Solution Approach 2:
Sacrificial nanosheet layers act as intermediary structures during fabrication. These temporary layers enable the formation of complex gate structures around nanosheet channels, then are selectively removed to create the final transistor architecture. The intermediary sacrificial layers facilitate the creation of high-density devices without requiring direct formation of the complex final structure
2Reliability
If extended-gate structures are formed to tolerate larger threshold voltages, then gate voltage tolerance is improved, but device area increases
Solution Approach 1:
The gate structure transitions from a planar configuration to a three-dimensional extended-gate configuration that wraps around the nanosheet channels. This dimensional change allows the gate to provide enhanced voltage control and tolerance without proportionally increasing the planar device footprint, as the additional gate material extends in the vertical and lateral dimensions around the channel
3Adaptability or versatility
If multiple transistor types are integrated on the same substrate, then device versatility is improved, but process compatibility challenges increase
Solution Approach 1:
A universal nanosheet-based fabrication platform is established that can produce multiple transistor types (nanosheet FETs, extended-gate transistors, and memory devices) using the same initial nanosheet stack formation processes. Different device types are created by applying different subsequent processing steps to the same substrate regions, enabling multi-functionality while maintaining process compatibility through a common fabrication foundation
Solution Approach 2:
Different regions of the substrate are selectively processed to create different device types. The nanosheet stacks in various regions undergo different transformations - some regions receive extended-gate formation for high-voltage tolerance, others receive standard gate formation for normal operation, and some are converted to memory structures. This local differentiation allows versatile device integration while using uniform initial fabrication processes
Data Source
AI summary
Embodiments of the invention are directed to methods of fabricating devices on a substrate. A non-limiting example of the method includes performing memory fabrication operations to form a non-volatile memory device in a first region of the substrate, wherein the memory fabrication operations include forming a first region of a nanosheet stack over the first region of the substrate. The first region of the nanosheet stack includes nanosheet layers of a first type of semiconductor material alternating with nanosheet layers of a second type of semiconductor material. A first portion of the first region of the nanosheet stack is replaced with a control gate of the non-volatile memory device, and a charge trapping region of the non-volatile memory device is provided under the control gate.