Nanosheet Transistor Structure With Merged Epitaxy for Higher Density
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Solution Overview
Problem
The semiconductor industry faces challenges in improving processing and manufacturing efficiency as the complexity of semiconductor integrated circuits (ICs) increases with smaller geometries, leading to higher production costs and complexity.
Innovation Solution
The method involves forming a stack of semiconductor layers over a substrate, using alternating layers of different etch selectivity and oxidation rates, and employing advanced patterning and etching processes to create nanosheet transistors with optimized channel widths and gate electrode structures, which enhance device density and reduce electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but processing complexity increases
Solution Approach 1:
The patent segments the semiconductor structure into multiple thin semiconductor layers (e.g., five alternating layers with different etch selectivities) stacked between source/drain regions. This segmentation enables the formation of nanosheet channels with controlled dimensions and facilitates selective processing of individual layers, thereby managing processing complexity while achieving high device density and improved productivity.
Solution Approach 2:
The patent applies local quality by creating regions with different etch selectivities within the semiconductor stack. Specific layers are engineered to have enhanced etch selectivity relative to adjacent layers, allowing selective removal of sacrificial layers and precise definition of nanosheet channels. This local differentiation simplifies the patterning process and reduces overall processing complexity while maintaining high functional density.
2Quantity of substance
If functional density is increased with smaller geometries, then more devices per chip area are achieved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the active channel region into multiple discrete nanosheet channels formed from alternating semiconductor layers. Each layer can be processed independently through selective etching, enabling precise control over channel formation. This segmentation approach allows high device density to be achieved while managing manufacturing complexity through modular, layer-by-layer processing.
Solution Approach 2:
The patent transitions from planar device architecture to a vertical stacking configuration, where multiple nanosheet channels are arranged in the vertical dimension rather than expanding horizontally. This dimensional change enables increased functional density without proportionally increasing manufacturing complexity, as the same fabrication processes can be applied to each layer in the stack.
3Quantity of substance
If advanced patterning and etching processes are used to create nanosheet transistors, then device density increases, but processing complexity increases
Solution Approach 1:
The patent incorporates layers with locally enhanced etch selectivity within the semiconductor stack. These layers are specifically engineered to respond differently to etching processes, enabling selective removal of sacrificial layers and precise definition of nanosheet channels. This local quality differentiation simplifies the advanced patterning process by providing built-in processing guides, thereby reducing the overall complexity of creating high-density nanosheet transistor structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases device density, reduces electrical resistance, and lowers manufacturing costs by enabling more efficient production of complex semiconductor devices with improved performance.
Implementation Method 1
using alternating layers of different etch selectivity and oxidation rates
Implementation Method 2
using alternating layers of different etch selectivity and oxidation rates
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.