Nanosheet Transistor Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge in the semiconductor industry is to further improve the performance of nanosheet FETs as transistor dimensions continue to scale down, requiring advancements in materials and manufacturing processes to enhance device density, performance, and reduce costs.
Innovation Solution
The proposed solution involves a semiconductor device structure manufacturing process that includes forming a stack of semiconductor layers with alternating first and second semiconductor layers, an etch stop layer, and using epitaxial growth to form nanostructure channels. This process allows for the formation of strained germanium or silicon channel layers, which enhance channel mobility for both NMOS and PMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then production efficiency and cost are improved, but manufacturing complexity increases
Solution Approach 1:
The channel region is segmented into multiple nanosheets stacked vertically, with each nanosheet providing a separate conduction path. This segmentation allows the transistor to achieve higher device density through vertical stacking while maintaining manufacturability through standardized layer formation processes
Solution Approach 2:
The invention transitions from two-dimensional planar transistors to three-dimensional nanosheet structures by stacking multiple channel layers vertically. This dimensional change increases device density without proportionally increasing manufacturing complexity, as the vertical stacking can be achieved through conformal deposition and etching processes
2Productivity
If conventional nanosheet FET structures are used, then device density is improved, but channel mobility and performance are limited
Solution Approach 1:
Different semiconductor materials are used for different nanosheet layers depending on whether NMOS or PMOS devices are required. Silicon-based nanosheets are used for NMOS channels while germanium-based nanosheets are used for PMOS channels, optimizing carrier mobility for each device type while maintaining the vertical stacked structure
Solution Approach 2:
The device structure incorporates composite material stacks including silicon-germanium alloy layers, pure silicon nanosheets, and pure germanium nanosheets in alternating configurations. These composite structures enable tailored electrical properties for different device regions while maintaining structural integrity through the vertical stack
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes gate-to-source/drain parasitic capacitance and enhances channel mobility, leading to improved performance and efficiency in semiconductor devices.
Implementation Method 1
using epitaxial growth to form nanostructure channels
Implementation Method 2
forming strained germanium or silicon channel layers, which enhance channel mobility
Data Source
AI summary
Various embodiments of the present disclosure provide a semiconductor device structure including a source/drain feature disposed over a substrate, a plurality of semiconductor layers vertically stacked over the substrate and in contact with the source/drain feature, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a first dielectric spacer in contact with a first side of a topmost semiconductor layer of the plurality of semiconductor layers, and a second dielectric spacer in contact with a second side of the topmost semiconductor layer of the plurality of semiconductor layers.