Nano-Sheet Transistor Same-Depth Contacts
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Solution Overview
Problem
Modern integrated circuits require both NMOS and PMOS transistors, leading to increased cell area consumption due to the need for both device types in CMOS technology, necessitating a reduction in cell area without fundamental changes in fabrication processes.
Innovation Solution
The development of novel complementary nano-sheet/wire transistor devices with same depth contacts, involving a stack of semiconductor material layers, source/drain regions, and a gate structure with specific capacitively coupled portions, allowing for the formation of nano-sheet devices with reduced area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both NMOS and PMOS devices are arranged in a pattern to create functional units, then functional units can be created, but cell area increases
Solution Approach 1:
The patent transitions from planar transistor arrangements to vertically stacked three-dimensional devices. Multiple semiconductor layers (first semiconductor layer, second semiconductor layer) are stacked vertically with gate structures extending around them, enabling functional units to be created in the vertical dimension rather than only in the planar dimension. This dramatically reduces the cell area occupied by each functional unit while maintaining the ability to create both NMOS and PMOS devices.
2Area of stationary object
If smaller devices are fabricated to reduce cell area, then cell area is reduced, but fundamental changes in fabrication processes are required
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming the stack of semiconductor layers, creating gate structures, forming source/drain regions, and creating contacts. Each stage uses standard fabrication techniques applied to specific layers or regions. The stack itself is segmented into multiple semiconductor layers that can be processed independently before final integration, allowing complex 3D structures to be built using sequential application of simpler processes.
Solution Approach 2:
The patent introduces intermediate structures such as dielectric layers between source/drain regions, sacrificial layers during fabrication, and gate structures that mediate the formation of the final device. These intermediaries enable the creation of complex stacked structures using standard processes, as each intermediate layer facilitates the next fabrication step without requiring fundamental process changes.
3Reliability
If source/drain regions have increased overlap, then device functionality is maintained, but cell area increases
Solution Approach 1:
The patent resolves the overlap issue by moving the device structure into the vertical dimension. Source/drain regions are formed in different semiconductor layers at different vertical levels, with gate structures wrapping around them. This vertical separation eliminates the need for horizontal overlap between source/drain regions while maintaining electrical connectivity and device functionality through the three-dimensional gate control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reduction of cell area in integrated circuits by allowing for the fabrication of smaller transistor devices with reduced overlap between source/drain regions, thereby minimizing the overall area required for functional units.
Implementation Method 1
A gate structure has a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet
Data Source
AI summary
A device includes a first nano-sheet of a first semiconductor material. First source/drain regions are positioned adjacent ends of the first nano-sheet. A first dielectric material is positioned above the first source/drain regions. A second nano-sheet of a second semiconductor material is positioned above the first nano-sheet. Second source/drain regions are positioned adjacent ends of the second nano-sheet and above the first dielectric material. A gate structure has a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet. A first source/drain contact contacts a first portion of the second source/drain regions in a first region where the first and second source/drain regions do not vertically overlap. The first source/drain contact has a first depth that extends below a height of an upper surface of the first source/drain regions in a second region where the first and second source/drain regions vertically overlap.