Multi Threshold Voltage Nanosheet Transistors via Selective Dielectric Crystallization
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Solution Overview
Problem
The challenge in nanosheet transistor manufacturing is adjusting the threshold voltage due to the close spacing between channels, which limits design flexibility and device performance.
Innovation Solution
The solution involves selectively crystallizing the gate dielectric layer and using a dipole layer to modify the threshold voltage, allowing for the production of multiple threshold voltages without diffusing into the crystallized gate dielectric, thereby enhancing design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional techniques are used to adjust threshold voltage in nanosheet devices, then manufacturing process is simple, but design flexibility is limited due to close spacing between channels
Solution Approach 1:
The patent applies local quality by selectively crystallizing the gate dielectric layer in different regions to create multiple threshold voltages. Specifically, a first region has a crystallized gate dielectric layer while a second region has an amorphous gate dielectric layer, enabling different transistor threshold voltages in different areas of the same nanosheet device without changing the overall device structure
Solution Approach 2:
The patent changes the physical state parameter of the gate dielectric layer from amorphous to crystalline through selective thermal annealing. This parameter change (crystallization) modifies the electrical properties and threshold voltage of transistors in specific regions, providing design flexibility while using a single material system
2Adaptability or versatility
If multiple threshold voltages are implemented in nanosheet devices, then design flexibility increases, but additional processing steps and collateral damage increase
Solution Approach 1:
The patent merges multiple functions into a single gate dielectric layer by making it selectively crystallizable. The same gate dielectric layer serves both as the insulating layer for amorphous-region transistors and as the crystallizable precursor for high-threshold-voltage transistors, eliminating the need for separate dielectric layers and reducing processing steps
Solution Approach 2:
The patent performs preliminary action by forming a uniform gate dielectric layer across the entire nanosheet device before selective crystallization. This pre-formed layer is then selectively annealed in specific regions, avoiding the need to deposit multiple different dielectric materials and reducing overall processing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of nanosheet transistors with varied threshold voltages, improving device performance and design flexibility while minimizing additional processing steps and collateral damage.
Implementation Method 1
a crystallized gate dielectric layer surrounding the semiconductor channel layers of a first subset of the nanosheet stacks
Implementation Method 2
a gate dielectric modified by a diffused dipole material surrounding the semiconductor channel layers of a second subset of the nanosheet stacks
Data Source
AI summary
A semiconductor structure including nanosheet stacks on a substrate, each nanosheet stack including alternating layers of sacrificial semiconductor material and semiconductor channel material and a crystallized gate dielectric layer surrounding the semiconductor channel layers of a first subset of the nanosheet stacks, a dipole layer on top of the crystallized gate dielectric and surrounding the layers of semiconductor channel material of the first subset of the nanosheet stacks and a gate dielectric modified by a diffused dipole material surrounding the semiconductor channel layers of a second subset of the nanosheet stacks. A method including forming nanosheet stacks on a substrate, each nanosheet stack including alternating layers of sacrificial semiconductor material and semiconductor channel material, removing sacrificial semiconductor material layers of the set of nanosheet stacks, forming a gate dielectric surrounding the semiconductor channel layers of the nanosheet stacks, and crystalizing the gate dielectric of a subset of the nanosheet stacks.