Nanosheet Transistor Channel Structure for Short-Channel Control
Solution Overview
Problem
The reduction in size of transistors in semiconductor devices leads to short channel effects, which existing technologies have not effectively addressed.
Innovation Solution
A nanosheet field-effect transistor design is implemented, featuring a gate that surrounds the channel and includes upper and lower inner spacers, with protrusion portions that reduce direct contact between the channel ends, thereby alleviating short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to improve degree of integration, then device density increases, but short channel effects worsen
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional nanosheet channel structure with upper and lower protrusion portions. The gate wraps around the channel in multiple dimensions, providing enhanced electrostatic control that suppresses short channel effects while maintaining reduced transistor footprint for high integration density.
Solution Approach 2:
The gate structure is nested around the nanosheet channel, with the channel featuring upper and lower protrusion portions that extend into the gate region. This nested configuration maximizes gate control over the channel while minimizing the horizontal space required, enabling both high integration and effective short channel effect suppression.
2Reliability
If gate surrounds the channel to reduce short channel effects, then electrostatic control improves, but device complexity increases
Solution Approach 1:
The nanosheet channel is segmented into distinct regions including a base portion and upper/lower protrusion portions. This segmentation allows the gate to control different channel regions independently, improving electrostatic control while the modular structure facilitates systematic manufacturing processes.
Solution Approach 2:
The channel structure exhibits local quality variations with protrusion portions having different geometries at upper and lower regions. This localized structural differentiation optimizes electrostatic control at critical interfaces while maintaining manufacturing feasibility through region-specific process control.
Data Source
AI summary
A semiconductor device includes a first source/drain, a second source/drain isolated from direct contact with the first source/drain in a horizontal direction, a channel extending between the first source/drain and the second source/drain, a gate surrounding the channel, an upper inner spacer between the gate and the first source/drain and above the channel, and a lower inner spacer between the gate and the first source/drain and under the channel, in which the channel includes a base portion extending between the first source/drain and the second source/drain, an upper protrusion portion protruding upward from a top surface of the base portion, and a lower protrusion portion protruding downward from a bottom surface of the base portion, and a direction in which a top end of the upper protrusion portion is isolated from direct contact with a bottom end of the lower protrusion portion is oblique with respect to a vertical direction.