Nanosheet Transistor Trench Etching for Lower Channel Resistance
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Solution Overview
Problem
As integrated circuits continue to scale to smaller sub-micron sizes, it becomes increasingly challenging to reduce channel resistance while maintaining desired electric current for semiconductor devices.
Innovation Solution
The formation of nanosheet transistors with alternating semiconductor layers of different etch selectivity and oxidation rates, combined with a cyclic etching process using plasma etching and passivation steps, to create trenches with a straight and symmetric sidewall profile for improved channel structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar transistor structures are used, then manufacturing is simpler, but channel resistance increases and device performance deteriorates at sub-micron scales
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet channel structures with gate-all-around configuration. Multiple thin semiconductor layers are stacked vertically to form nanosheets, enabling the gate to surround the channel on all sides including top, bottom, and sidewalls, thus adding vertical dimensionality to improve electrostatic control and reduce channel resistance
Solution Approach 2:
The patent employs alternating stacks of different semiconductor materials (e.g., Si/SiGe, Si/SiN) with different etch selectivities and oxidation rates. These composite material structures enable selective removal of sacrificial layers to release individual nanosheet channels while maintaining structural integrity, achieving both complex 3D geometry and manufacturing feasibility
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency improves and costs decrease, but channel resistance reduction becomes increasingly challenging
Solution Approach 1:
By stacking multiple thin semiconductor layers vertically to form nanosheets, the patent achieves effective channel length reduction and increased functional density without proportionally reducing lithography dimensions. The vertical stacking allows more channels to be packed into the same footprint area, improving productivity while maintaining controllable channel resistance through gate-all-around geometry
Solution Approach 2:
The patent divides the channel into multiple discrete nanosheet segments stacked vertically, each surrounded by its own gate. This segmentation allows independent control of each channel layer and increases the total effective channel width within the same device footprint, thereby improving current drive capability and reducing effective channel resistance
3Ease of manufacture
If trenches with bowing sidewall profile are formed, then etching process is simpler, but channel resistance increases due to asymmetric structure
Solution Approach 1:
The patent employs a cyclic etching process with periodic alternation between etching steps and passivation steps. During etching, the sacrificial layers are removed; during passivation, the nanosheet surfaces are protected. This periodic action allows precise control of the etching front to maintain straight vertical sidewalls and symmetric trench profiles, ensuring low channel resistance while remaining manufacturable
Solution Approach 2:
The patent introduces sacrificial layers (e.g., SiGe, SiN) as intermediary structures between the semiconductor layers during fabrication. These sacrificial layers have different etch selectivity and are selectively removed to release the nanosheet channels. The intermediary sacrificial structures enable the formation of straight-walled trenches and symmetric profiles by providing a template that guides the etching process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces channel resistance and maintains desired electric current, enhancing the performance of semiconductor devices by optimizing the channel structure.
Implementation Method 1
performing a first etch process to form a trench with a first depth at a source/drain region of the fin structure... performing a second etch process to extend the trench from the first depth to a second depth
Implementation Method 2
passivating exposed surfaces of the trench to modify an etch selectivity of the exposed surfaces to a second etchant
Data Source
AI summary
Various embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes removing, using a first etchant, a portion of a fin structure at a source/drain region to form a trench with a first depth, passivating exposed surfaces of the trench to modify an etch selectivity of the exposed surfaces to a second etchant, subjecting the passivated surfaces to a treatment process, and removing, using the second etchant, the passivated surface and a portion of the fin structure to form the trench with a second depth that is greater than the first depth.