Nanosheet Transistors with Variable Channel Widths
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Solution Overview
Problem
The production of nanosheet device features at production nodes below 5 nm faces challenges such as excessive power consumption and issues with forming gate contacts, with known tapering techniques affecting epitaxial growth and etching processes.
Innovation Solution
The techniques disclosed maximize spacing for the deposition of an increased volume of gate dielectric in nanosheet FET structures, accommodating input and/or output devices by using multiple nanosheet regions with varying channel widths and dielectric isolators to optimize gate structure formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet devices are scaled to smaller dimensions below 5 nm to increase effective channel width per footprint area, then integration density is improved, but power consumption becomes excessive and gate contact formation becomes difficult
Solution Approach 1:
The patent divides the nanosheet structure into multiple discrete nanosheets within the channel, allowing independent control and optimization of each nanosheet's contribution to current. This segmentation enables better management of power consumption while maintaining high integration density through vertical stacking.
Solution Approach 2:
The patent transitions from planar device scaling to three-dimensional vertical stacking of nanosheets. By moving into the vertical dimension, the device achieves higher effective channel width and integration density without further reducing the lateral footprint, thereby avoiding the power consumption penalties associated with extreme lateral scaling.
2Use of energy by moving object
If known tapering techniques are used to reduce effective channel width for long power devices, then power consumption is reduced, but epitaxial growth of source/drain regions and etching processes are adversely affected
Solution Approach 1:
The patent applies different channel widths to different devices within the same nanosheet stack. By selectively forming gates around individual nanosheets or groups of nanosheets, the structure achieves local variation in effective channel width, allowing long power devices to have reduced width only where needed while maintaining uniform nanosheet dimensions throughout, thus preserving epitaxial growth and etching quality.
Data Source
AI summary
A semiconductor structure comprises a substrate defining a first axis and a second axis orthogonal to the first axis, a first nanosheet region disposed on the substrate and defining a first channel width along the second axis, a first gate disposed around the first nanosheet region, a second nanosheet region disposed on the substrate and defining a second channel width along the second axis less than the first channel width of the first nanosheet region and a second gate disposed around the second nanosheet region.