Nanosheet Transistors on Bulk Substrates with Localized Gate Isolation
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Solution Overview
Problem
Nanosheet transistors on bulk material substrates face challenges with leakage currents due to the lack of physical isolation between the nanosheet and the bulk material, which is not addressed by traditional semiconductor-on-insulator substrates.
Innovation Solution
A method involving a layered nanosheet structure with alternating sacrificial and semiconductor layers on a bulk substrate, where anisotropic etching creates trenches for insulating layer deposition, and epitaxial growth of source/drain regions with masking layers to isolate the nanosheet gates from the bulk substrate, reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If semiconductor-on-insulator (SOI) substrates are used to provide physical isolation for nanosheet transistors, then leakage currents are reduced, but production cost increases
Solution Approach 1:
The bulk substrate is segmented into multiple regions: a gate region with nanosheet transistors, source/drain regions, and isolation trenches. This segmentation allows selective isolation of the nanosheet gates from the bulk substrate while maintaining cost-effectiveness by using bulk material instead of expensive SOI substrates.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the nanosheet gates and the bulk substrate. This insulating layer provides the necessary electrical isolation to reduce leakage currents while allowing the use of cheaper bulk substrates instead of expensive SOI substrates.
2Ease of manufacture
If nanosheet transistors are formed on bulk material without isolation, then production cost is reduced, but control over electronic transport in the channel region deteriorates due to increased leakage currents
Solution Approach 1:
An insulating layer is introduced as an intermediary between the nanosheet gates and the bulk substrate. This insulating layer provides the necessary electrical isolation to reduce leakage currents while allowing the use of cheaper bulk substrates instead of expensive SOI substrates.
Solution Approach 2:
Isolation is applied locally only where needed - specifically in the gate region where nanosheet transistors are formed - rather than using expensive SOI substrates throughout the entire device. The insulating layer is deposited selectively in trenches formed in the bulk substrate, providing localized isolation to improve electronic transport control while maintaining cost-effectiveness.
3Object-generated harmful factors
If trenches are created through anisotropic etching to deposit insulating layers, then isolation between nanosheet gates and bulk substrate is improved, but device complexity increases
Solution Approach 1:
The isolation structure is created by etching trenches vertically into the bulk substrate and then depositing insulating layers within these trenches. This three-dimensional approach to isolation provides effective electrical separation between the nanosheet gates and the bulk substrate while maintaining a relatively simple overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively isolates nanosheet gates from the bulk material, reducing leakage currents and enhancing control over electronic transport in the channel region, while maintaining cost-effectiveness by using bulk substrates instead of more expensive semiconductor-on-insulator substrates.
Implementation Method 1
anisotropically etching the starting substrate located between the plurality of gates. Etching the starting substrate creates a trench through the layered nanosheet and the buffer sacrificial layer and into the bulk substrate
Implementation Method 2
epitaxial growth of source/drain regions
Data Source
AI summary
A semiconductor structure. The structure includes first source/drain located in a first source/drain region. The structure includes a second source/drain located in a second source/drain region. The structure includes a plurality of semiconductor nanosheets located between the first source/drain and the second source/drain in a gate region. The structure includes an insulating layer separating the first source drain from a bulk substrate. The bulk substrate may have a first horizontal surface in the gate region, a second horizontal surface in the first source/drain region, and a connecting surface forming an at least partially vertical connection between the first horizontal surface and the second horizontal surface. The insulating layer may be directly on the second horizontal surface and the connecting surface.