Nanosheet Transistors with Inner Airgaps for Strain Engineering
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Solution Overview
Problem
Current semiconductor technologies face challenges in scaling beyond the 7 nm node due to limitations in nanosheet formation processes, particularly in achieving high-quality epitaxial growth and strain introduction for nanosheet transistors, which affect device performance and efficiency.
Innovation Solution
The method involves forming a nanosheet stack with alternating layers of materials, creating sacrificial spacers and airgaps through selective etching and epitaxial growth of source/drain regions, allowing for improved epi quality and strain introduction, and using a sacrificial spacer process to form airgaps in both gate and inner spacer regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional nanosheet formation processes are used, then device fabrication is simpler, but epitaxial growth quality and strain introduction are insufficient
Solution Approach 1:
The nanosheet stack is segmented into alternating layers of first material and second material, allowing selective processing of each layer type. This segmentation enables precise control over epitaxial growth in specific regions while maintaining overall structural integrity, resolving the contradiction between growth quality and process simplicity.
Solution Approach 2:
Dummy gates and sacrificial spacers are formed in advance before the main fabrication steps. These preliminary structures serve as templates and protection layers that enable subsequent high-quality epitaxial growth and strain introduction, while the overall process remains manageable through pre-planned sequence execution.
2Reliability
If airgaps are added to reduce parasitic capacitance, then device performance improves, but fabrication process becomes more complex
Solution Approach 1:
Sacrificial spacers and dummy gates serve as intermediary structures that enable airgap formation. These temporary structures are formed, processed, and then removed to create the desired airgaps. The intermediaries make the complex airgap formation process manageable by breaking it into controlled steps that can be integrated into existing fabrication flows.
3Manufacturing precision
If inner spacers are used to define cavities, then source/drain region precision improves, but manufacturing steps increase
Solution Approach 1:
The formation of inner spacers is merged with the existing sacrificial spacer process flow. Both structures are formed using similar deposition and etching techniques, allowing parallel processing and reducing the overall impact on fabrication throughput. The merged approach maintains precision while minimizing productivity loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the construction of nanosheet transistors with enhanced channel strain and high-quality embedded source/drain epitaxy, reducing parasitic capacitance and improving device performance for logic and high-voltage applications.
Implementation Method 1
selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material
Implementation Method 2
epitaxially growing source/drain regions adjacent the nanosheet stack
Implementation Method 3
selectively removing the sacrificial spacers and the inner spacers to define cavities
Data Source
AI summary
A method is presented for constructing a nanosheet transistor. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a dummy gate over the nanosheet stack, forming sacrificial spacers adjacent the dummy gate, and selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material. The method further includes filling the gaps with inner spacers, epitaxially growing source/drain regions adjacent the nanosheet stack, selectively removing the sacrificial spacers and the inner spacers to define cavities, and filling the cavities with a spacer material to define first airgaps adjacent the dummy gate and second airgaps adjacent the etched alternating layers of the first material.