Nanosheet Transistors With Segmented Sacrificial Layers
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Solution Overview
Problem
The critical thickness of sacrificial silicon germanium layers in nanowire and nanosheet transistors limits the spacing between channel layers, making it difficult to pattern gate workfunction metals and form thick gate oxide transistors due to strain and defects, and aggressive etching is required to remove workfunction metal from narrow gaps, leading to undesirable undercuts.
Innovation Solution
The use of multiple sacrificial layers with etch selectivity allows for forming thick oxide gate dielectrics and patterning workfunction metals by increasing the separation between channel layers beyond the critical thickness of the sacrificial material, using a multilayer structure of silicon germanium, doped silicon, and another sacrificial material to prevent dopant diffusion and strain, and forming inner spacers for gate conductor placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the spacing between channel layers is increased beyond the critical thickness of sacrificial material, then thicker gate dielectrics and different workfunction metals can be formed, but the lattice mismatch between silicon germanium and silicon crystals causes strain and defects in the sacrificial layers
Solution Approach 1:
The patent divides the single thick sacrificial layer into multiple thinner sacrificial layers separated by channel layers. Each sacrificial layer is kept below the critical thickness to avoid defect formation, while the cumulative spacing between channel layers achieves the desired larger separation. This segmentation allows the structure to benefit from increased channel spacing without exceeding the critical thickness limit of individual sacrificial layers.
Solution Approach 2:
The patent applies different materials and thicknesses to different regions of the sacrificial structure. Specifically, it uses silicon germanium sacrificial layers with controlled thicknesses and compositions tailored to local requirements, ensuring that each region maintains structural integrity while achieving the overall goal of increased channel spacing.
2Manufacturing precision
If the spacing between channel layers is small, then the critical thickness of sacrificial material is reduced, but it becomes difficult to pattern gate workfunction metals and form thick gate oxide transistors
Solution Approach 1:
By segmenting the sacrificial structure into multiple layers, the patent creates sufficient vertical spacing between channel layers to accommodate thick gate dielectrics and workfunction metal patterns, while keeping each individual sacrificial layer thin enough to avoid defects.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking multiple channel layers separated by sacrificial layers, transforming a two-dimensional planar structure into a three-dimensional vertically stacked structure. This dimensional change provides the necessary space for gate formation while maintaining control over sacrificial layer thickness.
3Ease of manufacture
If aggressive etching is used to remove workfunction metal from narrow gaps, then the workfunction metal can be removed, but undesirable undercuts are created between adjacent transistors
Solution Approach 1:
The segmented structure with increased spacing between channel layers creates larger gaps that allow for less aggressive etching processes, removing the need for extreme etching conditions that cause undercuts.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures that facilitate the formation and removal of workfunction metals. These sacrificial layers provide a buffer that allows for controlled etching processes without directly exposing the channel layers to aggressive etchants.
Data Source
AI summary
Integrated chips include vertically stacked channel layers, with a first stack in a first device region and a second stack in a second device region. A first dielectric layer is formed conformally on the vertically stacked channel layers in the first device region. A second dielectric layer is formed conformally on the vertically stacked channel layers in the second device region. Gate conductors are formed around the vertically stacked channel layers in both the first device region and the second device region, filling a space between surfaces of the respective first dielectric layer and second dielectric layer.