Nanosheet Transistors With Vertical Stacked Source Drain Regions
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Solution Overview
Problem
Current semiconductor device fabrication techniques face challenges in achieving high packing density and low power consumption in integrated circuits due to limitations in control over carrier flow and leakage current in planar field-effect transistors, which are addressed by developing nanosheet field-effect transistors with a gate-all-around arrangement.
Innovation Solution
The proposed solution involves forming a structure with multiple nanosheet channel layers stacked in a three-dimensional array, where sacrificial layers are etched to release the nanosheet channel layers and create spaces for a gate stack, and a complementary field-effect transistor configuration with vertically stacked source/drain regions and a functional gate structure to enhance control over carrier flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar field-effect transistors are used, then manufacturing is simpler, but packing density is lower and leakage current is higher
Solution Approach 1:
The patent transitions from planar (2D) field-effect transistors to three-dimensional vertically stacked nanosheet transistors. Multiple nanosheet channel layers are stacked vertically to form a three-dimensional array structure, enabling increased packing density by utilizing the vertical dimension while maintaining manufacturing feasibility through adapted fabrication processes
2Device complexity
If planar field-effect transistors are used, then device structure is simpler, but control over carrier flow is reduced
Solution Approach 1:
The gate structure completely surrounds each nanosheet channel layer in a nested configuration, with the gate electrode wrapping around the channel from all sides. This gate-all-around arrangement provides superior control over carrier flow in the channel by eliminating uncontrolled interfaces, achieving enhanced reliability while managing device complexity through systematic structural design
3Quantity of substance
If vertically stacked nanosheet transistors are formed, then packing density increases, but manufacturing complexity increases
Solution Approach 1:
The transistor structure is segmented into multiple discrete nanosheet channel layers stacked vertically, with each layer independently formed and controlled. This segmentation allows for increased packing density while managing manufacturing complexity by treating each nanosheet as a separate controllable unit in the vertical stack
Solution Approach 2:
The invention moves from two-dimensional planar transistor layouts to three-dimensional vertically stacked configurations. Multiple nanosheet channel layers are arranged in the vertical dimension, significantly increasing packing density while adapting manufacturing processes to accommodate the three-dimensional architecture
4Reliability
If gate-all-around structure is implemented, then control over channel is improved, but device complexity increases
Solution Approach 1:
The gate electrode is nested around each nanosheet channel layer in a complete surround configuration, with the gate structure enveloping the channel from all sides. This nested gate-all-around arrangement provides maximum control over carrier flow in the channel by eliminating any uncontrolled interfaces, achieving superior channel control while managing device complexity through systematic structural design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased packing density and reduced leakage current, leading to improved performance and lower power consumption in integrated circuits by providing precise control over the channel and enhancing the 'Off' state performance of field-effect transistors.
Implementation Method 1
The sacrificial layers are etched and removed in order to release the nanosheet channel layers, and to provide spaces for the formation of the gate stack
Data Source
AI summary
Structures and circuits including multiple nanosheet field-effect transistors and methods of forming such structures and circuits. A complementary field-effect transistor includes a first nanosheet transistor with a source/drain region and a second nanosheet transistor with a source/drain region stacked over the source/drain region of the first nanosheet transistor. A contact extends vertically to connect the source/drain region of the first nanosheet transistor of the complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the complementary field-effect transistor.