Nanosheet Semiconductor Structure With Vertical Contacts for Reliable Scaling
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Solution Overview
Problem
As semiconductor devices downscale, they face challenges in achieving high operation speeds and accuracy while minimizing process defects, particularly in nanosheet field-effect transistors, which can lead to performance and reliability issues.
Innovation Solution
The semiconductor device design includes a fin-type active region with horizontal and vertical semiconductor layers, a seed layer, and a gate line structure that surrounds the horizontal semiconductor layer, where the vertical semiconductor layers contact the horizontal layer and seed layer, enhancing the channel region and source/drain regions for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If semiconductor devices downscale to increase integration density, then device size is reduced, but process defects increase and reliability deteriorates
Solution Approach 1:
The channel region is divided into multiple nanosheet layers stacked vertically, allowing the device to maintain a compact footprint while providing multiple conduction paths. This segmentation increases effective channel area without increasing device footprint, thereby improving reliability despite downsaling
Solution Approach 2:
The invention transitions from planar 2D channel structures to vertically stacked 3D nanosheet structures. By utilizing the vertical dimension, the device achieves higher integration density while maintaining robust electrical characteristics through multiple stacked channels, resolving the reliability concern associated with downsaling
2Productivity
If nanosheet field-effect transistors are manufactured with reduced sizes, then integration density increases, but process defects occur more frequently
Solution Approach 1:
The gate structure is formed to completely surround each nanosheet layer before final device completion. This preliminary gate formation ensures precise control over each individual nanosheet, reducing variability and process defects that typically arise in later manufacturing stages
Solution Approach 2:
Multiple nanosheet layers are nested vertically within a compact footprint, with each layer surrounded by its own gate structure. This nested configuration achieves high integration density while maintaining manufacturability, as the vertical stacking reduces the lateral processing complexity compared to planar high-density designs
3Reliability
If vertical semiconductor layers are added to contact horizontal layers, then electrical performance improves, but device complexity increases
Solution Approach 1:
Contact regions extend vertically to reach multiple stacked nanosheet channels, utilizing the vertical dimension to provide electrical access. This vertical contact approach improves electrical performance by directly accessing multiple channels without requiring complex lateral routing, thereby managing structural complexity while enhancing reliability
Data Source
AI summary
A semiconductor device includes a fin-type active region that extends in length in a first horizontal direction on a substrate, a horizontal semiconductor layer on the fin-type active region, a seed layer on the fin-type active region and in contact with the horizontal semiconductor layer, a gate line that surrounds the horizontal semiconductor layer and the seed layer, on the fin-type active region, and that extends in length in a second horizontal direction that intersects the first horizontal direction, and a pair of vertical semiconductor layers respectively on first and second sides of the horizontal semiconductor layer in the first horizontal direction, on the fin-type active region, with the horizontal semiconductor layer therebetween, wherein an inner wall of each of the first and second vertical semiconductor layers contacts the horizontal semiconductor layer, and upper or lower surfaces of the vertical semiconductor layers contact the seed layer.