Nanosheet Via Layout for Dense IC Routing Without Shorting
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Solution Overview
Problem
As integrated circuit (IC) devices scale down, it becomes challenging to increase metal line packing density while maintaining low resistance and preventing leakage or shorting between conductive features, which hinders device performance optimization and increases processing complexity.
Innovation Solution
The proposed solution involves optimizing the design of nano-sheet-based devices by minimizing feature resistances and mitigating shorting concerns through specific configurations of gate vias and metal lines, allowing for maximized metal line density without compromising device integrity or routing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC dimensions are reduced to improve production efficiency and lower costs, then productivity increases, but manufacturing precision requirements increase and process complexity increases
Solution Approach 1:
The patent transitions from planar 2D device structures to three-dimensional nanosheet-based devices with gate-all-around configuration. This dimensional change enables better gate control over the channel while maintaining scaled dimensions, thereby improving manufacturing precision requirements without sacrificing productivity gains from scaling
2Productivity
If metal line packing density is increased to improve routing efficiency, then productivity increases, but resistance increases and shorting risk increases
Solution Approach 1:
The patent implements a multi-layer interconnect structure where metal lines are arranged in stacked layers with via structures connecting them. This nesting approach allows increased routing capacity and packing density while maintaining adequate spacing between conductive features in each layer, thereby preventing shorting and maintaining reliability
Solution Approach 2:
The patent utilizes vertical stacking of metal interconnect layers to increase routing efficiency. By moving from planar routing to three-dimensional stacked routing, the system achieves higher packing density without increasing in-plane resistance or shorting risk, as each layer maintains proper isolation
3Productivity
If feature size is reduced to improve production efficiency, then productivity increases, but device performance optimization becomes more difficult
Solution Approach 1:
The patent divides the channel into multiple thin nanosheet segments stacked vertically, each surrounded by its own gate structure. This segmentation allows each nanosheet to be independently controlled and optimized, simplifying the processing of individual features while achieving enhanced overall device performance through the stacked configuration
Solution Approach 2:
The patent addresses processing complexity by moving to a vertical stacking architecture where multiple nanosheet devices are formed in the vertical dimension rather than requiring complex planar patterning at ultra-fine dimensions. This dimensional transition maintains productivity benefits while reducing the complexity of individual feature fabrication
Data Source
AI summary
A device includes a substrate having a top surface, a fin extending lengthwise along a first direction, a source feature and a drain feature, a gate structure having a gate stack extending along a second direction perpendicular to the first direction and interposing between the source and drain features, a gate via directly disposed on the gate stack, a source via electrically connecting the source feature, and a drain via electrically connecting the drain feature. The fin includes a stack of channel layers engaged by the gate stack. The source via has a first dimension along the second direction and a second dimension along the first direction, the drain via feature has a third dimension along the second direction and a fourth dimension along the first direction. A ratio of the first dimension to the second dimension is greater than a ratio of the third dimension to the fourth dimension.