Nanosheet Via Layout for Dense Routing Without Gate Spacer Shorts
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Solution Overview
Problem
The challenge of increasing metal line packing density in integrated circuits while minimizing resistance and mitigating shorting concerns in nano-sheet-based devices has become increasingly complex, particularly as feature dimensions shrink, affecting device performance and processing efficiency.
Innovation Solution
The proposed solution involves optimizing the placement and design of gate vias and metal lines in nano-sheet-based devices, ensuring they are positioned to avoid shorting risks and maximize routing efficiency by allowing the gate vias to be placed on the active region without intruding onto gate spacers, and matching via dimensions to metal line dimensions to minimize resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate vias are placed on the active region to maximize routing efficiency, then routing efficiency is improved, but shorting risk increases
Solution Approach 1:
The patent applies local quality by differentiating via placement rules based on location: gate vias are permitted on the active region (providing routing efficiency) but prohibited from intruding onto gate spacers (preventing shorting). This spatial differentiation of via placement permissions resolves the contradiction between routing efficiency and shorting risk.
2Productivity
If metal line packing density is increased to improve production efficiency, then production efficiency is improved, but resistance increases
Solution Approach 1:
The patent applies parameter changes by optimizing via dimensions to match metal line dimensions, which minimizes resistance at via-metal line interfaces. This parameter optimization allows for increased metal line packing density while controlling resistance, thereby resolving the contradiction between production efficiency and resistance.
3Productivity
If feature dimensions are reduced to improve production efficiency, then production efficiency is improved, but processing complexity increases
Solution Approach 1:
The patent applies preliminary action by establishing clear via placement rules and dimension matching requirements before the actual manufacturing process. These pre-defined guidelines simplify the processing of reduced-featured devices by providing explicit design constraints, thereby resolving the contradiction between improved production efficiency from scaling and increased processing complexity.
Data Source
AI summary
A device includes a substrate having a top surface, a fin extending lengthwise along a first direction, a source feature and a drain feature, a gate structure having a gate stack extending along a second direction perpendicular to the first direction and interposing between the source and drain features, a gate via directly disposed on the gate stack, a source via electrically connecting the source feature, and a drain via electrically connecting the drain feature. The fin includes a stack of channel layers engaged by the gate stack. The source via has a first dimension along the second direction and a second dimension along the first direction, the drain via feature has a third dimension along the second direction and a fourth dimension along the first direction. A ratio of the first dimension to the second dimension is greater than a ratio of the third dimension to the fourth dimension.