Nanosheet Fabrication via Wafer Bonding and Debonding
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Solution Overview
Problem
Conventional nanosheet fabrication methods, such as epitaxial growth of Si/SiGe stacks, face limitations in achieving uniform thickness and width due to poor selectivity ratios and critical thickness constraints, leading to defects and suboptimal electrostatic control in semiconductor devices.
Innovation Solution
The method involves using silicon-on-insulator (SOI) technology to form defect-free nanosheets by bonding and debonding wafers with alternating silicon and dielectric layers, allowing for independent tuning of thickness and spacing, and using high etch selectivity between silicon and silicon dioxide to achieve precise control over nanosheet shape and thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional epitaxial growth of Si/SiGe stacks is used, then nanosheets can be formed, but thickness uniformity deteriorates due to poor selectivity ratio and critical thickness constraints
Solution Approach 1:
The fabrication process is segmented into multiple independent steps: forming sacrificial layers, forming conduction layers, selective removal of sacrificial layers, and release. This segmentation allows each step to be optimized independently, achieving uniform nanosheet thickness while maintaining process feasibility.
Solution Approach 2:
Sacrificial layers (silicon dioxide or silicon nitride) are introduced as intermediary materials that enable precise thickness control. These sacrificial layers act as spacers during formation and are selectively removed later, allowing the conduction layers to be released as free-standing nanosheets with uniform thickness without being constrained by critical thickness limits.
2Quantity of substance
If nanosheet thickness is increased beyond critical thickness, then more material is available for conduction, but defects increase due to lattice mismatch
Solution Approach 1:
Sacrificial layers serve as mediators that enable the formation of thick nanosheets without lattice mismatch defects. By using sacrificial layers with different etch selectivity, the conduction layers can be grown thicker than the critical thickness while maintaining defect-free structures, as the sacrificial layers prevent misfit dislocation formation during growth.
3Reliability
If nanosheets are made wider to improve electrostatic control, then device performance improves, but parasitic capacitance increases due to larger gate-to-drain overlap
Solution Approach 1:
The sacrificial layers are selectively removed (taken out) from between the conduction layers, releasing the nanosheets as free-standing structures. This extraction eliminates the need for spacer materials between nanosheets, reducing parasitic capacitance while maintaining wide nanosheet widths for improved electrostatic control.
4Ease of manufacture
If selective etching is used to release nanosheets, then nanosheets can be separated, but thickness control deteriorates due to poor selectivity ratio between Si and SiGe
Solution Approach 1:
Sacrificial layers made of silicon dioxide or silicon nitride are introduced as intermediary materials that provide high etch selectivity. These sacrificial layers can be selectively removed using HF-based solutions or plasma etching without affecting the silicon or silicon-germanium conduction layers, enabling easy nanosheet release while maintaining precise thickness control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of substantially defect-free, uniformly thick, and wide nanosheets with no thickness restrictions, improving electrostatic control and device performance by maintaining rectangular nanosheet shape and reducing parasitic capacitance.
Implementation Method 1
bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure
Implementation Method 2
debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nanosheets and a plurality of dielectric layers alternately stacked
Implementation Method 3
using high etch selectivity between silicon and silicon dioxide to achieve precise control over nanosheet shape and thickness
Data Source
AI summary
Methods of forming nanosheets for a semiconductor device are provided including providing a silicon on insulator (SOI) handle wafer, the SOT handle wafer including a silicon layer and a dielectric layer on the silicon layer; providing a first donor wafer; bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure; debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nanosheets and a plurality of dielectric layers alternately stacked; and bonding the intermediate wafer to a second donor wafer to provide a final wafer including a plurality of silicon or non-silicon layers and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of silicon or non-silicon and dielectric layers than the intermediate wafer.