Nanosheet Work Function Metal Patterning for Lower Gate Capacitance
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Solution Overview
Problem
The scaling of features in integrated circuits faces challenges such as gate overburden leading to parasitic capacitance and difficulties in patterning work function metals (WFMs) in nanosheet technology, which affect the performance and density of semiconductor devices.
Innovation Solution
A semiconductor device fabrication method involving the formation of dual layer top dielectric caps (TDCs) with high-k dielectric and WFMs, followed by recessing the gate metal and WFMs to minimize gate overburden, thereby reducing parasitic capacitance and improving WFM patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate metal and WFMs are formed with full coverage, then device performance is improved, but gate overburden increases leading to parasitic capacitance
Solution Approach 1:
The gate structure is segmented into multiple sections with varying WFM thicknesses. The gate metal is divided into first and second portions, where the first portion has a first WFM thickness and the second portion has a second WFM thickness, allowing different regions to serve different functions while reducing overall parasitic capacitance
Solution Approach 2:
Different regions of the gate structure are assigned different WFM thicknesses based on local requirements. The first WFM portion provides necessary work function characteristics in critical areas, while the second WFM portion has reduced thickness to minimize parasitic capacitance in non-critical areas
2Ease of manufacture
If WFM is patterned with conventional methods, then manufacturing simplicity is maintained, but patterning difficulties arise in nanosheet technology
Solution Approach 1:
A mandrel structure is formed beforehand to guide the sequential deposition and patterning of WFMs. The mandrel serves as a pre-established template that enables precise WFM patterning through subsequent deposition and etching steps, eliminating the need for complex direct patterning methods
Solution Approach 2:
The mandrel acts as an intermediary structure that facilitates WFM patterning. It enables the formation of complex WFM patterns through sequential deposition and selective removal, serving as a temporary guide that simplifies the overall patterning process
3Quantity of substance
If device density is increased through scaling, then capacity is improved, but gate overburden and parasitic capacitance worsen
Solution Approach 1:
The gate structure is segmented into multiple sections with varying WFM thicknesses. The gate metal is divided into first and second portions, where the first portion has a first WFM thickness and the second portion has a second WFM thickness, allowing different regions to serve different functions while reducing overall parasitic capacitance
Solution Approach 2:
The WFM thickness parameter is varied across different regions of the gate structure. By changing the thickness parameter from a uniform value to a spatially varying value (first thickness in first portion, second thickness in second portion), the structure achieves both high device density and reduced parasitic capacitance
Data Source
AI summary
A semiconductor device fabrication method is provided and includes forming first and second stacks each including a dual layer top dielectric cap (TDC), sequentially surrounding each layer and a portion of the dual layer TDC of the first stack with high-k dielectric, a first work function metal (WFM) and a second WFM, sequentially surrounding each layer and a portion of the dual layer TDC of the second stack with the high-k dielectric and the second WFM, forming gate metal around the first and second stacks and recessing the gate metal and the second WFM to a depth defined above a height of an uppermost first WFM horizontal portion.