Nanosheet Work Function Metal Patterning for Low-Capacitance Contacts

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Solution Overview

Problem

The scaling of semiconductor devices to smaller features poses challenges such as electrostatic issues, mobility degradation, and difficulties in controlling the channel, particularly in nanostructure FETs, where gate overburden leads to parasitic capacitance and patterning of nanosheet work function metals is difficult.

Innovation Solution

A semiconductor device fabrication method involving the formation of first and second gate stacks with a dual layer top dielectric cap, sequentially surrounding each layer with high-k dielectric and work function metals, followed by the formation of gate metal and recessing it to a depth above the uppermost work function metal horizontal portion, thereby minimizing gate overburden and improving patterning accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If gate metal and WFMs are formed with full coverage, then device performance is improved, but gate overburden increases leading to parasitic capacitance

Engineering Contradiction:
Improvedevice performanceVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The gate structure is segmented into multiple sections with varying WFM thicknesses. The gate metal is divided into first and second portions, where the first portion has a first WFM thickness and the second portion has a second WFM thickness, allowing different regions to serve different functions while reducing overall parasitic capacitance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the gate structure are assigned different WFM thicknesses based on local requirements. The first WFM portion provides necessary work function characteristics in critical areas, while the second WFM portion has reduced thickness to minimize parasitic capacitance in non-critical areas

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If WFM is patterned with conventional methods, then manufacturing simplicity is maintained, but patterning difficulties arise in nanosheet technology

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidWFM patterning difficulty
Core Design Contradiction:
Ease of manufactureVSDifficulty of detecting and measuring

Solution Approach 1:

A mandrel structure is formed beforehand to guide the sequential deposition and patterning of WFMs. The mandrel serves as a pre-established template that enables precise WFM patterning through subsequent deposition and etching steps, eliminating the need for complex direct patterning methods

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The mandrel acts as an intermediary structure that facilitates WFM patterning. It enables the formation of complex WFM patterns through sequential deposition and selective removal, serving as a temporary guide that simplifies the overall patterning process

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If device density is increased through scaling, then capacity is improved, but gate overburden and parasitic capacitance worsen

Engineering Contradiction:
Improvedevice densityVSAvoidparasitic capacitance
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The gate structure is segmented into multiple sections with varying WFM thicknesses. The gate metal is divided into first and second portions, where the first portion has a first WFM thickness and the second portion has a second WFM thickness, allowing different regions to serve different functions while reducing overall parasitic capacitance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The WFM thickness parameter is varied across different regions of the gate structure. By changing the thickness parameter from a uniform value to a spatially varying value (first thickness in first portion, second thickness in second portion), the structure achieves both high device density and reduced parasitic capacitance

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250031414A1Work function metal patterning and middle-of-line self-aligned contacts for nanosheet technology
Publication Date: 2025.01.23 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20250031414A1 patent drawing
  • US20250031414A1 patent drawing
  • US20250031414A1 patent drawing

AI summary

A semiconductor device fabrication method is provided and includes forming first and second stacks each including a dual layer top dielectric cap (TDC), sequentially surrounding each layer and a portion of the dual layer TDC of the first stack with high-k dielectric, a first work function metal (WFM) and a second WFM, sequentially surrounding each layer and a portion of the dual layer TDC of the second stack with the high-k dielectric and the second WFM, forming gate metal around the first and second stacks and recessing the gate metal and the second WFM to a depth defined above a height of an uppermost first WFM horizontal portion.