Nanosheet Work Function Metal Removal via Organic Planarization

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Solution Overview

Problem

Conventional methods for removing work function metal (WFM) layers between n-type and p-type nanosheet devices in semiconductor manufacturing cause damage and limit the minimum distance and width of nanosheets, hindering the advancement of device density and performance in applications like SRAM.

Innovation Solution

The method involves alternatingly stacking WFM layers with nanosheet portions, using mask layers and an organic planarization layer to protect and replace WFM layers, ensuring precise removal and replacement without damaging adjacent WFM, thereby allowing closer spacing and increased width of nanosheet devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional lateral etching is used to remove work function metal layers between nanosheets, then work function metal can be removed, but adjacent work function metal layers are damaged and unwanted removal occurs

Engineering Contradiction:
Improvework function metal layer removal precisionVSAvoidadjacent work function metal integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent introduces an organic planarization layer as an intermediary protective barrier between the etchant and the work function metal layers. This layer is selectively removed to expose only the work function metal that needs to be removed, while protecting adjacent work function metal layers from damage. The organic planarization layer acts as a mediator that enables precise material removal without harmful side effects.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If extensive over-etching is performed to remove work function metal layers between nanosheets, then complete removal is achieved, but the minimum distance between n-type and p-type nanosheet devices is limited

Engineering Contradiction:
Improvework function metal layer removal completenessVSAvoidminimum distance between nanosheet devices
Core Design Contradiction:
Manufacturing precisionVSLength of moving object

Solution Approach 1:

The patent applies local quality by making the protective organic planarization layer non-uniform in thickness or presence across different regions. The layer is strategically positioned to protect work function metal only in regions where adjacent nanosheet devices are located, while allowing complete removal in regions between device types. This localized protection enables extensive over-etching where needed without limiting device spacing.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If conventional etching methods are used for work function metal removal, then processing can be completed, but the width of nanosheets is undesirably limited

Engineering Contradiction:
Improveetching process completionVSAvoidnanosheet width
Core Design Contradiction:
Ease of manufactureVSArea of moving object

Solution Approach 1:

The organic planarization layer serves as a protective intermediary that prevents etchant damage to nanosheet edges during the work function metal removal process. By placing this protective layer over the nanosheet regions, the etching process can proceed more aggressively and completely without compromising nanosheet integrity, thereby enabling increased nanosheet width.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10615257B2Patterning method for nanosheet transistors
Publication Date: 2020.04.07 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10615257B2 patent drawing
  • US10615257B2 patent drawing
  • US10615257B2 patent drawing

AI summary

A semiconductor device includes a first type nanosheet device having a first plurality of nanosheet portions alternately stacked with a first plurality of work function metal layers on a substrate, and a second type nanosheet device having a second plurality of nanosheet portions alternately stacked with a second plurality of work function metal layers on the substrate. The second type nanosheet device is spaced apart from the first type nanosheet device. The semiconductor device also includes a dielectric layer disposed in the space between the first and second type nanosheet devices. The first and second plurality of work function metal layers are directly disposed on the dielectric layer, and bottom surfaces of the directly disposed first and second plurality of work function metal layers are co-planar with each other.