Nanostructure Transistor Air-Gap Spacers Using SiGe Temporary Layers

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Solution Overview

Problem

As semiconductor devices shrink in size, nanostructure transistors face challenges such as short channel effects, increased electron tunneling, and fabrication issues, particularly in forming air gaps during the manufacturing of dielectric spacer layers, which can cause damage to the transistor components.

Innovation Solution

Incorporating a silicon germanium (SiGe) temporary spacer layer during the manufacturing process to facilitate the selective removal of sacrificial silicon dioxide (SiO2) spacer layers, thereby reducing damage to dielectric spacer layers and metal gate structures, and simplifying the fabrication of nanostructure transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If air gaps are formed during the manufacturing of dielectric spacer layers, then the fabrication process can be simplified, but damage to transistor components occurs

Engineering Contradiction:
Improvefabrication processVSAvoidtransistor components
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A silicon germanium (SiGe) temporary spacer layer is introduced as an intermediary between the sacrificial SiO2 spacer layer and the metal gate structure. This temporary layer acts as a mediator that protects the metal gate structure from damage during the air gap formation process, while still allowing the fabrication process to proceed with simplified air gap creation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The SiGe temporary spacer layer is formed in advance before the air gap formation process. This preliminary action prepares a protective barrier that prevents damage to the metal gate structure during subsequent manufacturing steps, particularly during the removal of sacrificial layers and formation of air gaps.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If sacrificial SiO2 spacer layers are removed to form air gaps, then device performance is improved, but damage to metal gate structures increases

Engineering Contradiction:
Improvedevice performanceVSAvoiddamage to metal gate structures
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The SiGe temporary spacer layer serves as a protective intermediary that remains in place during the removal of sacrificial SiO2 spacer layers. This intermediary layer shields the metal gate structure from mechanical and chemical damage that would otherwise occur during the air gap formation process, enabling safe removal of sacrificial materials.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The SiGe temporary spacer layer provides beforehand cushioning protection to the metal gate structure. By being positioned adjacent to the metal gate before the air gap formation process, it cushions and absorbs the harmful effects of the removal process, preventing direct contact between damaging forces and the metal gate structure.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Productivity

If technology processing nodes are reduced, then transistor density increases, but short channel effects worsen

Engineering Contradiction:
Improvetransistor densityVSAvoidshort channel effects
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The invention introduces a SiGe temporary spacer layer with specific local properties adjacent to the metal gate structure. This localized modification provides targeted protection in the critical region where the metal gate meets the air gap, allowing density improvements at smaller nodes while maintaining reliability through localized quality enhancement rather than global process changes.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250366147A1Semiconductor device and methods of formation
Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250366147A1 patent drawing
  • US20250366147A1 patent drawing
  • US20250366147A1 patent drawing

AI summary

Some implementations described herein provide techniques and semiconductor devices in which a dielectric region is included in a nanostructure transistor. The dielectric region, which may correspond to an air gap, may be located between dielectric spacer layers located along a sidewall of a metal gate structure. Techniques to form the dielectric region may include using a temporary spacer layer between the dielectric spacer layers during manufacturing of the nanostructure transistor. The temporary spacer layer may include a silicon germanium material having a reaction mechanism that allows the temporary spacer layer to be selectively removed without causing damage to the dielectric spacer layers, the metal gate structure, or other portions of the nanostructure transistor.