Nanostructure Transistors Using Air Inner Spacers to Limit Epitaxy Defects
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Solution Overview
Problem
The formation of nano-structure transistors with dielectric inner spacers results in high defect density due to epitaxy growth from these spacers, adversely affecting integrated circuit performance.
Innovation Solution
The use of air inner spacers formed between epitaxy source/drain regions and dielectric inner spacers, achieved by laterally recessing sacrificial layers and epitaxially growing the source/drain regions, reduces defect density and improves transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric inner spacers are formed to isolate epitaxy source/drain regions from gate stacks, then isolation is achieved, but epitaxy growth from the inner spacers causes high defect density
Solution Approach 1:
The patent removes the dielectric inner spacer material to create an air-filled space. This extraction eliminates the harmful epitaxy growth from dielectric surfaces while maintaining the isolation function. The air inner spacer is formed by removing the original dielectric inner spacer after gate stack formation, preventing contact between epitaxy source/drain regions and any spacer material.
Solution Approach 2:
The patent replaces the dielectric inner spacer with an air-filled space, creating an inert environment that does not support epitaxy growth. Air acts as an inert barrier that prevents unwanted material deposition and epitaxial growth on the inner spacer surface, thereby eliminating the defect generation mechanism while maintaining structural isolation.
2Object-generated harmful factors
If air inner spacers are formed by removing dielectric inner spacers, then defect density is reduced, but additional process steps are required
Solution Approach 1:
The patent performs the inner spacer removal at an optimal point in the process sequence - after gate stack formation but before final epitaxy completion. This preliminary action ensures that the air inner spacer is already in place to prevent defect formation during subsequent epitaxy growth, while leveraging existing process steps to minimize additional complexity.
3Strength
If dielectric inner spacers are used, then structural support is provided, but epitaxy growth from spacers creates defects
Solution Approach 1:
The patent extracts the dielectric inner spacer material entirely, replacing it with an air-filled space. This removal eliminates the source of harmful epitaxy growth while the air space itself provides sufficient structural support and isolation. The gate stack and surrounding structures maintain mechanical integrity without requiring a filled inner spacer.
Solution Approach 2:
The patent changes the physical state of the inner spacer from solid dielectric material to gaseous air. This parameter change fundamentally alters the interaction with epitaxy growth - air does not support epitaxial deposition like dielectric surfaces do, thereby eliminating defect formation while maintaining the spacer's dimensional and isolation functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of air inner spacers leads to fewer defects and enhanced performance of Gate All-Around (GAA) transistors by minimizing epitaxy-related defects, thereby improving the overall functionality of integrated circuits.
Implementation Method 1
laterally recessing the plurality of sacrificial layers to form lateral recesses
Implementation Method 2
epitaxially growing a source/drain region from the plurality of semiconductor nano structures, wherein the source/drain region is spaced apart from the inner spacers by air inner spacers
Data Source
AI summary
A method includes forming a stack of layers, which includes a plurality of semiconductor nano structures and a plurality of sacrificial layers. The plurality of semiconductor nano structures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, forming inner spacers in the lateral recesses, and epitaxially growing a source/drain region from the plurality of semiconductor nano structures. The source/drain region is spaced apart from the inner spacers by air inner spacers.