Nanostructure Anti-Fuse Memory Doping to Reduce Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing anti-fuse memory devices suffer from leakage current issues due to p-n junctions at the intersection of source/drain and channel, leading to increased programming voltage requirements and reduced performance and lifetime.
Innovation Solution
The implementation of nanostructure transistors with a floating source/drain doped in a reverse conduction type, which reduces or eliminates the p-n junction, thereby minimizing gate leakage current and allowing for successful programming without increasing the programming voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional anti-fuse memory devices are used with standard doping types, then the device structure is simple, but leakage current increases due to p-n junctions at the intersection of source/drain and channel
Solution Approach 1:
The patent applies reverse doping by doping the floating source/drain region with a doping type opposite to the channel doping type. Specifically, if the channel is p-type doped, the floating source/drain is n-type doped, and vice versa. This inversion eliminates the formation of p-n junctions at the source/drain-channel intersections, thereby reducing leakage current while maintaining device functionality.
2Use of energy by moving object
If standard source/drain doping is used, then the manufacturing process is straightforward, but programming voltage requirements increase due to leakage current
Solution Approach 1:
By inverting the doping type of the floating source/drain relative to the channel, the patent eliminates leakage paths that would otherwise require higher programming voltages to overcome. This reduces the energy required for programming operations.
Solution Approach 2:
The patent changes the doping type parameter of the floating source/drain region from matching the channel doping type to being opposite to it. This parameter change fundamentally alters the electrical characteristics, reducing leakage current and thereby lowering the programming voltage requirements.
3Reliability
If p-n junctions are present at source/drain-channel intersections, then the device structure is conventional, but performance and lifetime are reduced due to leakage current
Solution Approach 1:
The patent inverts the doping type of the floating source/drain region to be opposite to the channel doping type, thereby eliminating p-n junctions at their intersections. This removal of harmful p-n junctions reduces leakage current, improving both device performance and lifetime, while the doping configuration remains relatively simple and manufacturable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces gate leakage current, enabling efficient programming of anti-fuse memory cells while maintaining performance and extending the lifetime of the memory device.
Implementation Method 1
a first drain/source structure coupled to a first end of each of the plurality of first nanostructures, a second drain/source structure coupled to both of a second end of each of the plurality of first nanostructures and a first end of each of the plurality of second nanostructures, and a third drain/source structure coupled to a second end of each of the plurality of second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type opposite to the first doping type.
Data Source
AI summary
A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.