Nanostructure Gate Dielectric Etching With TMN Selectivity
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits (ICs) has increased complexity and damage to dielectric layers in nanostructure devices, particularly at corners and during etching processes, leading to reliability issues and performance degradation.
Innovation Solution
A high-selectivity wet etching process is employed to etch metal without removing the dielectric layer, using higher H2O2 concentration and slight acidic addition to improve dielectric film quality, reducing damage and enhancing the reliability of nanostructure transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used to remove metal layers, then metal removal is achieved, but dielectric layer damage occurs particularly at corners
Solution Approach 1:
The patent applies parameter changes by modifying the etchant composition (using acidic etchants with controlled HF content) and process conditions (temperature, time) to achieve selective removal of metal while preserving the dielectric layer. This resolves the contradiction by tuning etching parameters to differentiate between metal and dielectric etch rates.
Solution Approach 2:
The patent introduces an intermediary protective layer or modifies the etching process to include intermediate steps that protect the dielectric layer during metal removal. This mediator approach prevents direct harmful interaction between the etchant and dielectric corners.
2Productivity
If geometry size is decreased to increase functional density, then production efficiency improves, but processing complexity increases
Solution Approach 1:
The patent employs self-aligned processes where previously formed structures automatically serve as alignment references for subsequent steps. This self-service approach reduces the need for complex external alignment procedures, thereby simplifying processing despite reduced geometry sizes.
Solution Approach 2:
The patent segments the fabrication process into distinct modular steps with clear interfaces, allowing each step to be optimized independently. This segmentation manages processing complexity by breaking down the overall complex process into manageable, repeatable units.
3Area of stationary object
If scaling down continues to increase functional density, then chip area utilization improves, but stress concentration in dielectric layers increases
Solution Approach 1:
The patent applies local quality by providing enhanced protection or modified material properties specifically at stress-prone locations such as dielectric corners and interfaces. This localized approach addresses stress concentration without requiring global changes to the entire dielectric structure.
Solution Approach 2:
The patent implements beforehand cushioning by introducing protective layers or stress-relief structures prior to subsequent processing steps that would otherwise induce stress. This preventive measure cushions the dielectric layer against future stress concentration.
4Manufacturing precision
If wet etching with high H2O2 concentration is used, then metal etching selectivity improves, but dielectric layer removal risk increases
Solution Approach 1:
The patent carefully balances parameter changes by optimizing H2O2 concentration within a specific range and combining it with controlled acidic components. This parameter optimization achieves high metal etching selectivity while maintaining dielectric layer stability through balanced chemical interactions.
Solution Approach 2:
The patent uses composite etchant formulations combining H2O2 with specific acids and additives that provide synergistic effects. The composite composition enhances metal removal selectivity while the constituent components work together to protect the dielectric layer from unwanted removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves SRAM yield, reduces leakage current, increases mobility, enhances ring oscillator performance, and extends device lifetime by minimizing dielectric layer degradation and stress concentration effects.
Implementation Method 1
performing a second etch using an oxidizing etchant
Implementation Method 2
performing a first etch using an acidic etchant
Data Source
AI summary
A method includes: forming a stack of alternating first semiconductor channels and second semiconductor layers on a substrate; releasing the first semiconductor channels by removing the second semiconductor layers; forming a gate dielectric on the first semiconductor channels; forming a transition metal nitride layer on the gate dielectric; and exposing the gate dielectric in a first region of the substrate by removing the transition metal nitride layer. The removing includes: performing a first etch using an acidic etchant; and after the performing a first etch, performing a second etch using an oxidizing etchant.