Nanostructure ESD Structure With PIN Diodes for Lower Trigger Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the semiconductor industry, the removal of the device substrate for forming backside interconnect structures increases the complexity and difficulty of electrostatic discharge (ESD) protection, particularly due to limited bulk current and high trigger voltage in ESD snapback devices, which compromises performance, power, area, and cost of IC chips.
Innovation Solution
The integration of a PIN diode string between the base and collector of an intrinsic bipolar junction transistor (iBJT) within nanosheets on the IC chip reduces snapback trigger voltage and enhances ESD immunity, with the iBJT structure being scalable and compatible with both backside and frontside power processes, and the use of PIN diodes adjusts for different base biases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the device substrate is removed to form backside interconnect structures, then routing flexibility is improved, but ESD protection performance deteriorates due to high trigger voltage
Solution Approach 1:
The ESD protection device is segmented into multiple components: an intrinsic bipolar junction transistor (iBJT) with collector, base, and emitter regions, and a PIN diode string with multiple diodes connected in series. This segmentation allows independent optimization of each component's function while maintaining overall ESD protection capability in the substrate-less architecture
Solution Approach 2:
The PIN diode string acts as an intermediary element connected between the collector and base of the iBJT. This intermediary structure modifies the electrical characteristics of the ESD device, enabling lower trigger voltage and improved snapback performance while maintaining compatibility with backside interconnect processes
2Ease of manufacture
If conventional ESD devices are used in substrate-less structures, then manufacturing simplicity is maintained, but trigger voltage becomes excessively high
Solution Approach 1:
The invention changes key electrical parameters of the ESD device by introducing the PIN diode string and configuring the iBJT structure. This results in a reduced trigger voltage and improved snapback characteristics while maintaining compatibility with existing manufacturing processes for both frontside and backside power configurations
3Reliability
If ESD protection is implemented in advanced technology nodes, then device performance is improved, but leakage current increases
Solution Approach 1:
The ESD protection device uses locally optimized structures with specific doping profiles and geometric configurations in the iBJT and PIN diode regions. This local quality optimization enables effective ESD protection while minimizing leakage current through precise control of electrical properties in critical regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution improves ESD immunity, reduces on-resistance, and enhances the performance, power, and area efficiency of IC chips by lowering leakage current and improving metal routing, while being compatible with various processing methods.
Implementation Method 1
Device having nanostructure electrostatic discharge structure and method
Data Source
AI summary
A device includes a first circuit region including a nanostructure device and a second circuit region offset from the first circuit region. The nanostructure device has a vertical stack of nanostructures disposed in a plurality of first semiconductor layers and a gate structure wrapping around the nanostructures of the vertical stack. The second circuit region includes a bipolar junction device electrically connected to the nanostructure device and at least one diode electrically connected between a collector and a base of the bipolar junction device. At least one implant region extends through the plurality of first semiconductor layers and a plurality of second semiconductor layers that are disposed between respective vertically neighboring pairs of the plurality of first semiconductor layers. A backside interconnect structure is electrically connected to a source/drain region of the nanostructure device.