Nanostructure Fabrication via Thermal Surface Migration
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Solution Overview
Problem
Current methods for fabricating nanostructures in semiconductor devices are limited by lithography precision, which restricts the creation of structures less than 10 nm and prevents vertical organization, making it difficult to achieve precise control over dimensions and positioning for industrial-scale production.
Innovation Solution
A method involving the fabrication of a stack with alternating semiconductor portions, followed by thermal treatment to induce surface migration of atoms, allowing for the auto-organized formation of nanostructures with controlled dimensions and positioning, enabling the creation of nanostructures less than 10 nm with precise control over their depth and dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithography is used to fabricate nanostructures, then the fabrication process is simple and suitable for industrial production, but the minimum dimensions are limited to about 10 nm and vertical organization is not achievable
Solution Approach 1:
The patent replaces the mechanical lithography system with a self-organizing chemical system. Nanostructures are formed through spontaneous organization of materials during deposition, eliminating the need for lithographic patterning. This substitution enables sub-10 nm precision and vertical organization while simplifying the fabrication process.
Solution Approach 2:
The patent employs self-organizing mechanisms where materials automatically arrange into nanostructures during the deposition process. The system self-organizes to form vertically stacked nanostructures with precise dimensions and positioning without requiring external lithographic guidance, achieving both high precision and simplified fabrication.
2Manufacturing precision
If bottom-up methods are used to make nanostructures, then individual nanostructures can be fabricated with high precision, but the method is not suitable for industrial fabrication due to low productivity
Solution Approach 1:
The patent merges the advantages of top-down and bottom-up approaches by combining self-organizing material deposition with scalable industrial fabrication techniques. Multiple nanostructures are formed simultaneously in a single deposition process, maintaining high precision while achieving industrial-level productivity.
Solution Approach 2:
The patent transitions from two-dimensional lithographic patterning to three-dimensional self-organizing deposition. Nanostructures are formed vertically stacked in multiple layers, enabling precise dimensional control in all three dimensions while facilitating parallel fabrication of numerous structures, thereby achieving both high precision and high productivity.
3Ease of manufacture
If top-down lithography and etching are used, then the fabrication process is well-established, but nanostructure dimensions less than 10 nm cannot be achieved and vertical organization is prevented
Solution Approach 1:
The patent replaces the mechanical lithography and etching sequence with a direct self-organizing deposition process. This substitution maintains ease of manufacture by using standard deposition equipment while achieving superior dimensional precision and vertical organization that lithography cannot provide.
Solution Approach 2:
Instead of starting with a planar substrate and adding features through lithography, the patent inverts the approach by directly depositing self-organizing materials that spontaneously form vertical nanostructures. This inversion enables both sub-10 nm precision and vertical organization while maintaining fabrication simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the precise control of nanostructure dimensions and positioning, enabling the fabrication of organized nanostructures along vertical surfaces and at the nanoscale, suitable for advanced semiconductor devices like GAA-FET and SET transistors, with the potential for industrial-scale production.
Implementation Method 1
thermal treatment of the stack at a temperature which causes at least one surface migration of atoms of the second semiconductor from the second portion towards at least one part of the first portions
Data Source
AI summary
A method of fabrication of a semiconductor device including implementation of fabrication of at least one stack made on a substrate, including at least one first portion of a first semiconductor and at least one second portion of a second semiconductor which is different from the first semiconductor, so the thickness of at least the first portion is substantially equal to the thickness of at least one nanostructure, and wherein the first or second semiconductor is capable of being selectively etched relative to the second or first semiconductor, respectively, fabrication, on a part of the stack, of external spacers and at least one dummy gate, etching of the stack such that the remaining parts of the first and second portions are arranged beneath the dummy gate and beneath the external spacers and form a stack of nanowires, after the etching of the stack, thermal treatment of the stack of nanowires.