Nanostructure FET Air-Gap Source/Drain Layout for Leakage Reduction
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise with increased fringing capacitance and leakage current due to reduced feature sizes, necessitating improvements in device integration and performance.
Innovation Solution
The formation of air gaps under the source/drain regions of nanostructure devices, achieved by creating openings in the fin structure and selectively growing epitaxial source/drain materials laterally, while inhibiting growth on dielectric layers, thereby reducing fringing capacitance and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but fringing capacitance and leakage current increase
Solution Approach 1:
The patent extracts the problematic fringing field effects by introducing air gaps that physically separate and isolate the source and drain regions. The air gap acts as an extracted insulating element that removes the harmful capacitive coupling between adjacent structures, thereby reducing fringing capacitance while maintaining the miniaturized geometry needed for high integration density
Solution Approach 2:
The patent applies local quality by creating air gaps specifically at critical locations where source and drain regions interface with adjacent structures. This localized modification of the dielectric environment (replacing solid dielectric with air)针对性地 reduces fringing capacitance and leakage current at the most problematic interfaces, while leaving other areas of the device unchanged to maintain overall device functionality and integration density
2Productivity
If feature sizes are reduced to improve integration density, then more components fit in a given area, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by forming air gaps during intermediate fabrication steps before final device completion. The air gaps are created using selective epitaxial growth or deposition processes that self-align with existing structures, establishing the insulating separation early in the manufacturing sequence. This preliminary structuring simplifies subsequent processing steps and reduces the precision requirements for later alignment-critical operations
Solution Approach 2:
The air gap serves as an intermediary structure that mediates between conflicting manufacturing requirements. By introducing this intermediate air-filled space, the patent decouples the dimensional constraints of miniaturized features from the electrical performance requirements, allowing standard manufacturing processes to achieve the necessary precision without directly confronting the tightest feature size tolerances
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces fringing capacitance and leakage current, enhancing the performance and integration density of semiconductor devices by allowing for more components to be integrated into a given area.
Implementation Method 1
converting an upper layer of the fin exposed by the source/drain openings into a seed layer by performing an implantation process
Implementation Method 2
selectively depositing a dielectric layer on the seed layer
Implementation Method 3
selectively growing a source/drain material on opposing sidewalls of the second semiconductor material exposed by the opening
Data Source
AI summary
A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure includes a fin and a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure over the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed at a bottom of the opening into a seed layer by performing an implantation process; selectively depositing a dielectric layer over the seed layer at the bottom of the opening; and selectively growing a source/drain material on opposing sidewalls of the second semiconductor material exposed by the opening.