Nanostructure FET Backside Source/Drain Contact Without Sacrificial Contacts
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Solution Overview
Problem
Existing semiconductor device fabrication processes face challenges in integrating a backside source/drain contact for nanostructure FETs, particularly due to the complexity of removing sacrificial contacts, which increases fabrication complexity.
Innovation Solution
A method is developed to fabricate nanostructure FETs with a backside source/drain contact by forming a conduit liner and an inner column within the insulating layer, allowing direct contact without a sacrificial S/D contact, using epitaxial growth and selective etching techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sacrificial contacts are used to form backside source/drain contacts in nanostructure FETs, then the backside contact integration is achieved, but the fabrication process complexity increases
Solution Approach 1:
The patent extracts and eliminates the sacrificial contact component from the fabrication process. Instead of using sacrificial contacts that require removal, the invention directly forms the backside source/drain contacts through selective etching of the insulating layer, thereby achieving backside contact integration while reducing fabrication process complexity
Solution Approach 2:
The patent performs preliminary actions by pre-forming the conduit liner structure within the insulating layer before final contact formation. This preliminary structuring enables subsequent direct contact formation without requiring sacrificial materials, simplifying the overall fabrication process while ensuring proper contact integration
2Ease of manufacture
If conventional planar FET structures are used, then the fabrication process is simpler, but the device density and performance are reduced
Solution Approach 1:
The patent transitions from conventional planar (2D) FET structures to three-dimensional non-planar structures by forming vertical conduit liners and backside contacts. This dimensional change enables nanosheet channel stacking, significantly increasing device density while maintaining fabrication feasibility through adapted process steps
3Reliability
If nanosheet channels with gate wrap-around are implemented, then the channel control is improved, but the fabrication complexity increases
Solution Approach 1:
The patent segments the source/drain contact formation into distinct components: a top contact region and a backside contact region with conduit liner. This segmentation allows independent optimization of each contact region, enabling improved channel control through gate wrap-around while managing fabrication complexity through modular contact structure formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process by eliminating the need for sacrificial contacts, reducing complexity and improving integration of backside S/D contacts in nanostructure FETs.
Implementation Method 1
using epitaxial growth and selective etching techniques
Implementation Method 2
using epitaxial growth and selective etching techniques
Data Source
AI summary
A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.