Nanostructure FET Backside Source/Drain Contact Without Sacrificial S/D

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Solution Overview

Problem

Existing nanostructure FET devices face complexity in integrating a backside source/drain (S/D) contact without a sacrificial S/D contact, which complicates semiconductor device fabrication.

Innovation Solution

A method of forming a semiconductor device with a backside S/D contact by creating a trench below the insulator layer and forming a second S/D region that extends below the top surface, eliminating the need for a sacrificial S/D contact by directly contacting the channel regions from the backside.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a backside S/D contact is integrated without a sacrificial S/D contact, then fabrication complexity is reduced, but the integration process becomes more difficult

Engineering Contradiction:

Improvefabrication complexityVSAvoidintegration difficulty

Core Design Contradiction:

Device complexityVSEase of manufacture

Solution Approach 1:

The patent applies inversion by forming the second S/D region from the backside of the substrate rather than from the front side. This reverse approach allows direct contact with the channel region without requiring a sacrificial S/D contact structure, thereby simplifying the fabrication process and reducing device complexity while maintaining ease of manufacture

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent transitions from a two-dimensional planar fabrication approach to a three-dimensional approach by accessing the channel region from the backside of the substrate. This dimensional change enables the formation of the second S/D region through the substrate thickness, allowing direct electrical contact without additional sacrificial structures and simplifying the overall integration process

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If a second S/D region extends below the insulator layer, then direct contact with channel regions is achieved, but fabrication process steps increase

Engineering Contradiction:

Improvecontact reliabilityVSAvoidfabrication efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary action by forming the second S/D region that extends below the insulator layer before final device assembly. This advance preparation ensures direct contact with the channel region is established early in the fabrication process, improving contact reliability while the subsequent steps complete the device formation efficiently

Inventive Principle:

Principle #10Preliminary action

3Reliability

If a liner is formed upon the insulator layer, then S/D region contact is improved, but manufacturing steps increase

Engineering Contradiction:

ImproveS/D contact qualityVSAvoidmanufacturing steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a liner as an intermediary layer between the insulator layer and the S/D regions. This liner improves the electrical contact quality and interface properties. While it adds one manufacturing step, the liner enables reliable S/D contact formation without requiring multiple complex process steps, thus improving reliability with minimal increase in device complexity

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20240112985A1Field effect transistor with backside source/drain

Publication Date: 2024.04.04 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extends vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region extends below a bottom surface of the gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.