Nanostructure FET Channel Doping for Lower Resistance
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in reducing electrical resistance and improving carrier mobility in channel regions of transistors.
Innovation Solution
An ion implantation process is performed to dope end portions of semiconductor material layers, forming doped regions with higher carrier mobility and lower electrical resistance, which are then used to form channel regions in nanostructure field-effect transistors (NSFETs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but electrical resistance in channel regions increases and carrier mobility decreases
Solution Approach 1:
The patent applies local quality by creating doped regions with different carrier concentrations in specific locations within the channel. High-concentration doped regions are formed at the source and drain ends of the channel, while the middle portion remains lightly doped or undoped. This spatial variation in doping concentration optimizes both electrical performance and integration density by reducing resistance at critical interfaces without compromising the overall device functionality.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but carrier mobility in channel regions decreases
Solution Approach 1:
The patent implements local quality by varying the doping concentration spatially within the channel region. High-concentration doped regions are created at the source and drain ends to facilitate carrier injection and extraction, while the channel middle portion maintains lower doping concentration to preserve carrier mobility. This localized differentiation allows the device to achieve high integration density while maintaining acceptable carrier mobility in the critical transport region.
3Reliability
If ion implantation is used to dope semiconductor layers, then doped regions with higher carrier mobility are formed, but the process complexity increases
Solution Approach 1:
The patent applies preliminary action by performing ion implantation doping at an early stage in the fabrication process, before other critical steps such as gate formation and dielectric deposition. By establishing the doped regions in the semiconductor layers beforehand, the process enables subsequent steps to proceed more efficiently and reduces the need for additional complex processing stages, thereby managing overall process complexity while achieving the desired carrier mobility enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces electrical resistance and improves the electrical performance of NSFET devices by creating doped regions with increased carrier mobility and reduced resistance in the channel regions.
Implementation Method 1
an ion implantation process is performed to implant a dopant into end portions of layers of a semiconductor material
Data Source
AI summary
A method of forming a semiconductor device includes: forming a fin structure that protrudes above a substrate, where the fin structure includes a fin and a layer stack overlying the fin, where the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; forming a gate structure over the fin structure; forming source/drain openings in the fin structure on opposing sides of the gate structure; replacing first end portions of the first semiconductor material exposed by the source/drain openings with inner spacers; after the replacing, performing an ion implantation process, where the ion implantation process implants a first dopant into second end portions of the second semiconductor material exposed by the source/drain openings; and after performing the ion implantation process, forming source/drain regions in the source/drain openings.