Nanostructure FET Gate Oxide Differentiation for Logic and I/O
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in integrating different electronic components with varying performance specifications, particularly in achieving different gate oxide thicknesses for logic and input/output device regions to manage leakage current and power consumption.
Innovation Solution
A method is disclosed to form nanostructures with varying gate oxide thicknesses by using a patterned hard mask layer to shield certain device regions from oxidation, allowing for differential thickness modulation in logic and I/O device regions, thereby achieving specific performance targets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform gate oxide thickness is formed across all device regions, then the manufacturing process is simple, but leakage current and power consumption cannot be optimized for different device types
Solution Approach 1:
The patent applies local quality by forming different gate oxide thicknesses in different device regions. Specifically, a first gate oxide thickness is formed in the logic device region while a second, different gate oxide thickness is formed in the I/O device region, allowing each region to be optimized for its specific functional requirements regarding leakage current and power consumption
Solution Approach 2:
The patent segments the semiconductor device into different device regions (logic device region and I/O device region) with distinct gate oxide thicknesses. This segmentation is achieved through region-specific oxidation processes that treat different areas differently, enabling independent optimization of each region's electrical characteristics
2Productivity
If the minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision and control over gate oxide thickness become more difficult
Solution Approach 1:
By implementing local quality through region-specific gate oxide formation, the patent enables precise control of electrical characteristics in each device region independent of feature size scaling. This allows advanced nodes with reduced minimum feature sizes to maintain manufacturing precision through localized process optimization rather than relying solely on global process control
Solution Approach 2:
The patent employs preliminary action by forming a gate oxide layer before patterning the gate electrode. This preliminary gate oxide formation establishes a foundation that enables subsequent precise thickness control in different regions through selective oxidation, facilitating better manufacturing precision at scaled dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with differentiated gate oxide thicknesses, enhancing leakage current and power consumption performance in different device regions, facilitating better integration and control of transistor devices.
Implementation Method 1
increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process
Data Source
AI summary
A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.